Á¤º¸Ã³¸®ÇÐȸ ³í¹®Áö ÄÄÇ»ÅÍ ¹× Åë½Å½Ã½ºÅÛ
Current Result Document :
ÇѱÛÁ¦¸ñ(Korean Title) |
FPGA¸¦ ÀÌ¿ëÇÑ 32-Bit RISC-V ÇÁ·Î¼¼¼ ¼³°è ¹× Æò°¡ |
¿µ¹®Á¦¸ñ(English Title) |
Design and Evaluation of 32-Bit RISC-V Processor Using FPGA |
ÀúÀÚ(Author) |
Àå¼±°æ
¹Ú»ó¿ì
±Ç±¸À±
¼Å¿ø
Sungyeong Jang
Sangwoo Park
Guyun Kwon
Taeweon Suh
|
¿ø¹®¼ö·Ïó(Citation) |
VOL 11 NO. 01 PP. 0001 ~ 0008 (2022. 01) |
Çѱ۳»¿ë (Korean Abstract) |
RISC-V´Â ¿ÀÇ ¼Ò½º ¸í·É¾î ÁýÇÕ ±¸Á¶·Î, °£´ÜÇÑ ±âº» ±¸Á¶¸¦ °¡Áö¸ç ¸ñÀû¿¡ µû¶ó ¸í·É¾î ÁýÇÕÀ» À¯¿¬ÇÏ°Ô È®ÀåÇÒ ¼ö ÀÖ´Ù. º» ³í¹®¿¡¼´Â ¼ÒÇü, ÀúÀü·Â 32-bit RISC-V ÇÁ·Î¼¼¼¸¦ ¼³°èÇÏ¿© RISC-V ÀÓº£µðµå ½Ã½ºÅÛ ¿¬±¸¸¦ À§ÇÑ ±â¹ÝÀ» ¸¶·ÃÇÏ°íÀÚ ÇÏ¿´´Ù. ¼³°èÇÑ ÇÁ·Î¼¼¼´Â 2´Ü°è ÆÄÀÌÇÁ¶óÀÎÀ¸·Î ±¸¼ºÇÏ¿´°í, RISC-V ISA Áß FENCE, EBREAK ¸í·É¾î¸¦ Á¦¿ÜÇÑ 32-bit Á¤¼öÇü ISA ¹× ÀÎÅÍ·´Æ® 󸮸¦ À§ÇÑ Æ¯±Ç ISA¸¦ Áö¿øÇÑ´Ù. Vivado Design Suite¸¦ ÀÌ¿ëÇÏ¿© ÇÕ¼ºÇÑ °á°ú Xilinx Zynq-7000 FPGA¿¡¼ 1895°³ÀÇ LUT ¹× 1195°³ÀÇ Çø³Ç÷ÓÀ» »ç¿ëÇÏ¿´°í, 0.001WÀÇ Àü·ÂÀ» ¼Ò¸ðÇÏ¿´´Ù. À̸¦ GPIO, UART, ŸÀÌ¸Ó¿Í ÇÔ²² ½Ã½ºÅÛÀ» ±¸¼ºÇÏ¿© ÇÕ¼ºÇÏ¿´°í, FPGA »ó¿¡¼ FreeRTOS¸¦ Æ÷ÆÃÇÏ¿© 16MHz¿¡¼ÀÇ µ¿ÀÛÀ» °ËÁõÇÏ¿´´Ù. Dhrystone, Coremark º¥Ä¡¸¶Å©¸¦ ÅëÇØ ¼º´ÉÀ» ÃøÁ¤ÇÏ¿© ¸ñÀû¿¡ µû¶ó È®Àå °¡´ÉÇÑ ÀúÀü·Â °íÈ¿À² ÇÁ·Î¼¼¼ÀÓÀ» º¸¿´´Ù. |
¿µ¹®³»¿ë (English Abstract) |
RISC-V is an open-source instruction set architecture which has a simple base structure and can be extensible depending on the purpose. In this paper, we designed a small and low-power 32-bit RISC-V processor to establish the base for research on RISC-V embedded systems. We designed a 2-stage pipelined processor which supports RISC-V base integer instruction set except for FENCE and EBREAK instructions. The processor also supports privileged ISA for trap handling. It used 1895 LUTs and 1195 flip-flops, and consumed 0.001W on Xilinx Zynq-7000 FPGA when synthesized using Vivado Design Suite. GPIO, UART, and timer peripherals are additionally used to compose the system. We verified the operation of the processor on FPGA with FreeRTOS at 16MHz. We used Dhrystone and Coremark benchmarks to measure the performance of the processor. This study aims to provide a low-power, high-efficiency microprocessor for future extension. |
Å°¿öµå(Keyword) |
RISC-V
FPGA
Processor
|
ÆÄÀÏ÷ºÎ |
PDF ´Ù¿î·Îµå
|