TIIS (한국인터넷정보학회)
Current Result Document :
| 한글제목(Korean Title) |
High Performance Integer Multiplier on FPGA with Radix-4 Number Theoretic Transform |
| 영문제목(English Title) |
High Performance Integer Multiplier on FPGA with Radix-4 Number Theoretic Transform |
| 저자(Author) |
Boon-Chiao Chang
Wai-Kong Lee
Bok-Min Goi
Seong Oun Hwang
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| 원문수록처(Citation) |
VOL 16 NO. 8 PP. 2816 ~ 2830 (2022. 8) |
한글내용
(Korean Abstract) |
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영문내용
(English Abstract) |
Number Theoretic Transform (NTT) is a method to design efficient multiplier for large integer multiplication, which is widely used in cryptography and scientific computation. On top of that, it has also received wide attention from the research community to design efficient hardware architecture for large size RSA, fully homomorphic encryption, and lattice-based cryptography. Existing NTT hardware architecture reported in the literature are mainly designed based on radix-2 NTT, due to its small area consumption. However, NTT with larger radix (e.g., radix-4) may achieve faster speed performance in the expense of larger hardware resources. In this paper, we present the performance evaluation on NTT architecture in terms of hardware resource consumption and the latency, based on the proposed radix-2 and radix-4 technique. Our experimental results show that the 16-point radix-4 architecture is 2× faster than radix-2 architecture in expense of approximately 4× additional hardware. The proposed architecture can be extended to support the large integer multiplication in cryptography applications (e.g., RSA). The experimental results show that the proposed 3072-bit multiplier outperformed the best 3k-multiplier from Chen et al. [16] by 3.06%, but it also costs about 40% more LUTs and 77.8% more DSPs resources. |
| 키워드(Keyword) |
Cryptography
FPGA
Number Theoretic Transform
Homomorphic Encryption
Lattice based Cryptosystem
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| 파일첨부 |
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