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ÇѱÛÁ¦¸ñ(Korean Title) |
µ¥ÀÌŸ ij½ÃÀÇ È°¿ëµµ¸¦ ³ôÀÌ´Â µ¿Àû ¼±ÀÎÃâ ÇÊÅ͸µ ±â¹ý |
¿µ¹®Á¦¸ñ(English Title) |
Dynamic Prefetch Filtering Schemes to enhance Utilization of Data Cache |
ÀúÀÚ(Author) |
Àü¿µ¼÷
±è¼®ÀÏ
ÀüÁß³²
Young-Suk Chon
SukIl Kim
Joongnam Jeon
|
¿ø¹®¼ö·Ïó(Citation) |
VOL 35 NO. 01 PP. 0030 ~ 0043 (2008. 02) |
Çѱ۳»¿ë (Korean Abstract) |
Load/store¿Í °°Àº ¸Þ¸ð¸® ÂüÁ¶ ¸í·É¾î´Â ÇÁ·Î¼¼¼ÀÇ °í¼Ó ¼öÇàÀ» ¹æÇØÇÏ´Â ÁÖ¿äÀÎÀÌ´Ù. ij½Ã ¼±ÀÎÃâ ±â¹ýÀº ¸Þ¸ð¸® ÂüÁ¶¿¡ µû¸¥ Áö¿¬½Ã°£À» ÁÙÀÌ´Â È¿°úÀûÀÎ ¹æ¹ýÀÌ´Ù. ±×·¯³ª ³Ê¹« Àû±ØÀûÀ¸·Î ¼±ÀÎÃâÇÒ °æ¿ì¿¡ ij½Ã ¿À¿°À» À¯¹ß½ÃÄÑ ¼±ÀÎÃâ¿¡ ÀÇÇÑ ÀåÁ¡À» »ó¼â½ÃŲ´Ù. º» ¿¬±¸¿¡¼´Â ij½ÃÀÇ ¿À¿°À» ÁÙÀ̱â À§ÇØ µ¿ÀûÀ¸·Î ÇÊÅÍ Å×À̺íÀ» ÂüÁ¶ÇÏ¿© ¼±ÀÎÃâ ¸í·ÉÀ» ¼öÇàÇÒ ÁöÀÇ ¿©ºÎ¸¦ °áÁ¤ÇÏ´Â ³× °¡Áö ÇÊÅ͸µ ±â¹ýµéÀ» ºñ±³ Æò°¡ÇÑ´Ù. ¸ÕÀú ±âÁ¸ ¿¬±¸¿¡¼ÀÇ ¹®Á¦Á¡À» ºÐ¼®Çϱâ À§ÇØ ÀÌÁø »óÅ ±â¹ýÀ» º¸¿´´Âµ¥, ÀÌ ±â¹ýÀº ±âÁ¸ ¿¬±¸¿Í °°ÀÌ N:1 ¸ÅÇÎÀ» »ç¿ëÇÏ´Â ¹Ý¸é, °¢ ¿£Æ®¸®ÀÇ °ªÀ» 1ºñÆ®·Î ÇÏ¿© µÎ °¡Áö »óÅ°ªÀ» °®µµ·Ï ÇÏ¿´´Ù. ºñ±³ ¿¬±¸¸¦ À§ÇØ ¿ÏÀü »óÅ ±â¹ýÀ» Á¦½ÃÇÏ¿© ºñ±³ ±âÁØÀ¸·Î »ç¿ëÇÏ¿´´Ù. ¸¶Áö¸·À¸·Î º» ³í¹®ÀÇ ÁÖ ¾ÆÀ̵ð¾îÀÎ Á¤±³ÇÑ ÇÊÅ͸µÀ» À§ÇÑ ºí·ÏÁÖ¼Ò ÂüÁ¶ ±â¹ýÀ» Á¦¾ÈÇÏ¿´´Ù. ÀÌ ±â¹ýÀº ÀÌÁø »óÅ ±â¹ý°ú °°Àº Å×ÀÌºí ±æÀ̸¦ °¡Áö¸ç, °¢ ¿£Æ®¸®ÀÇ ³»¿ëÀº ¿ÏÀü »óÅ ±â¹ý°ú °°Àº Ç׸ñÀ» °¡Áöµµ·Ï ÇÏ¿© ÃÖ±Ù¿¡ ¹Ì »ç¿ëµÈ µ¥ÀÌŸÀÇ ºí·ÏÁÖ¼Ò°¡ ÇÊÅÍ Å×À̺íÀÇ ÇϳªÀÇ ¿£Æ®¸®¿Í ´ëÀÀµÇµµ·Ï 1:1 ¸ÅÇÎÀ» ÇÏ¿´´Ù. ÀϹÝÀûÀ¸·Î ¸¹ÀÌ »ç¿ëµÇ´Â ÀÏ¹Ý º¥Ä¡¸¶Å© ÇÁ·Î±×·¥°ú ¸ÖƼ¹Ìµð¾î º¥Ä¡¸¶Å© ÇÁ·Î±×·¥µé¿¡ ´ëÇÏ¿© ½ÇÇèÇÑ °á°ú, Á¦¾ÈÇÑ ºí·ÏÁÖ¼Ò ÂüÁ¶ ±â¹ý(BAL)ÀÌ ±âÁ¸ ¿¬±¸ÀÎ µ¿Àû ÇÊÅÍ ±â¹ý(2-bitSC)°ú ºñ±³ÇÏ¿© ij½Ã ¹Ì½ºÀ²ÀÌ 10.5%°¨¼ÒÇÏ¿´´Ù. |
¿µ¹®³»¿ë (English Abstract) |
Memory reference instructions such as loads or stores are critical factors that limit the processing power of processor. The prefetching technique is an effective way to reduce the latency caused from memory access. However, excessively aggressive prefetch leads to cache pollution so as to cancel out the advantage of prefetch. In this study, four filtering schemes have been compared and evaluated which dynamically decide whether to begin prefetch after referring a filtering table to decrease cache pollution. First, A bi-states scheme has been shown to analyze the lock problem of the conventional scheme, this scheme such as conventional scheme used to be N:1 mapping, but it has the two state to 1bit value of each entries. A complete state scheme has been introduced to be used as a reference for the comparative study. A block address lookup scheme has been proposed as the main idea of this paper which exhibits the most exact filtering performance. This scheme has a length of the table the same as the bi-states scheme, the contents of each entry have the fields the same as the complete state scheme recently, never referenced data block address has been 1:1 mapping a entry of the filter table. Experimental results from commonly used general benchmarks and multimedia programs show that average cache miss ratio have been decreased by 10.5% for the block address lookup scheme(BAL) compare to conventional dynamic filter scheme(2-bitSC). |
Å°¿öµå(Keyword) |
ij½Ã ¸Þ¸ð¸®
¼±ÀÎÃâ ¾Ë°í¸®Áò
ÇÊÅ͸µ
cache memory
prefetch algorithm
filtering
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