2018³â ÄÄÇ»ÅÍÁ¾ÇÕÇмú´ëȸ
ÇѱÛÁ¦¸ñ(Korean Title) |
FPGA ±â¹Ý ¸ÖƼ ´º·² ³×Æ®¿öÅ© °¡¼Ó±â ÇÁ·¹ÀÓ¿öÅ© ¼³°è |
¿µ¹®Á¦¸ñ(English Title) |
Design of FPGA-based Multi-Neural Network Accelerator Framework |
ÀúÀÚ(Author) |
Xuan-Qui Pham
Tien-Dung Nguyen
Luan N.T. Huynh
and Eui-Nam Huh
ÀÌÀÎÈ£
È«¼º¹Î
·ù±âÇÏ
¹Ú¿µÁØ
Inho Lee
Seongmin Hong
Giha Ryu
Yongjun Park
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¿ø¹®¼ö·Ïó(Citation) |
VOL 45 NO. 01 PP. 1613 ~ 1615 (2018. 06) |
Çѱ۳»¿ë (Korean Abstract) |
´º·² ³×Æ®¿öÅ©´Â ´Ù¾çÇÑ ¾îÇø®ÄÉÀ̼ǿ¡¼ ³Î¸® »ç¿ëµÇ°í ÀÖ´Â ¾Ë°í¸®ÁòÀ¸·Î¼ ÀϹÝÀûÀÎ ´º·² ³×Æ®¿öÅ© °¡¼Ó±â´Â ÇÑ ¹ø¿¡ ÇÑ °¡ÁöÀÇ ¾îÇø®ÄÉÀ̼Ǹ¸À» Áö¿øÇϸç, ±×·¯¹Ç·Î ´ÙÁß ´º·² ³×Æ®¿öÅ© ¾îÇø®ÄÉÀ̼ÇÀ» ÀÌ¿ëÇϱâ À§Çؼ´Â °¡ÁßÄ¡(Weight), ÆíÇâ(Bias) µî °¢ ¾îÇø®ÄÉÀ̼ÇÀÇ Á¤º¸¸¦ ºü¸£°Ô ·ÎµùÇÒ ¼ö ÀÖ¾î¾ß ÇÑ´Ù. ÇÏÁö¸¸ FPGAÀÇ °æ¿ì ¿ÜºÎ ¸Þ¸ð¸®¿ÍÀÇ µ¥ÀÌÅÍ Àü¼Û ´ë¿ªÆø(Bandwidth)ÀÌ ³·¾Æ ÀÌ·¯ÇÑ °úÁ¤¿¡¼ Å« ¿À¹öÇìµå(Overhead)°¡ Á¸ÀçÇÑ´Ù. º» ¿¬±¸´Â ´Ù¼öÀÇ ´º·² ³×Æ®¿öÅ© ¾îÇø®ÄÉÀÌ¼Ç µ¥ÀÌÅÍ Á¤º¸¸¦ FPGA ³»ºÎÀÇ ¸Þ¸ð¸®¿¡ žÀçÇÏ¿© ´Ù¼öÀÇ ¾îÇø®ÄÉÀ̼ÇÀ» ºü¸£°Ô Áö¿øÇÒ ¼ö ÀÖ´Â FPGA ±â¹Ý ´º·² ³×Æ®¿öÅ© °¡¼Ó±â ¹× ÀÚµ¿È ÇÁ·¹ÀÓ¿öÅ©¸¦ Á¦½ÃÇÑ´Ù. À̸¦ À§ÇØ ÇϳªÀÇ ´º·² ³×Æ®¿öÅ© °¡¼Ó±â·Î ¿©·¯ °³ÀÇ ´º·² ³×Æ®¿öÅ© ¾îÇø®ÄÉÀ̼ÇÀ» ºü¸£°Ô º¯°æÇÏ¿© µ¿ÀÛÇÒ ¼ö ÀÖ´Â Çϵå¿þ¾î¸¦ ¼³°èÇÏ¿´À¸¸ç, ´º·² ³×Æ®¿öÅ©ÀÇ ¼ö, Àº´ÐÃþÀÇ ¼ö, ´º·±ÀÇ ¼ö µîÀÇ ÆĶó¹ÌÅ͸¦ ÅëÇØ ÀÚµ¿ÈµÈ ´º·² ³×Æ®¿öÅ© °¡¼Ó±â¸¦ ÇÕ¼ºÇÒ ¼ö ÀÖ´Â ÀÚµ¿È ÇÁ·¹ÀÓ¿öÅ©¸¦ ¼Ò°³ÇÑ´Ù.
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¿µ¹®³»¿ë (English Abstract) |
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Å°¿öµå(Keyword) |
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