ÇѱÛÁ¦¸ñ(Korean Title) |
ºÎÈ£À² º¯°æÀÌ °¡´ÉÇÑ BCH EcoderÀÇ FPGA±¸Çö |
¿µ¹®Á¦¸ñ(English Title) |
FPGA Implementation of BCH Encoder to change code rate |
ÀúÀÚ(Author) |
Á¦°¥µ¿
º¯°Ç½Ä
Dong Jegal
Kun-sik Byon
|
¿ø¹®¼ö·Ïó(Citation) |
VOL 13 NO. 01 PP. 0485 ~ 0489 (2009. 05) |
Çѱ۳»¿ë (Korean Abstract) |
º» ³í¹®¿¡¼´Â ºí·Ï ä³Î ºÎÈ£ °è¿¿¡¼ ´ÙÁß ¿À·ùÁ¤Á¤ ´É·ÂÀ» °®´Â BCH Encoder¸¦ FPGA·Î ±¸ÇöÇÑ ³í¹®ÀÌ´Ù. ¶ÇÇÑ ºÎÈ£À²ÀÇ º¯°æÀÌ °¡´ÉÇÏ°Ô ÇÏ¿© ´Ù¾çÈ ºÎÈ£ À²¿¡ µû¸¥ ºÎÈ£¸¦ »ý¼ºÇÒ ¼ö ÀÖ°Ô ÇÏ¿´´Ù. º» ³í¹®¿¡¼´Â FPGA ±¸ÇöÀ» À§ÇØ MatlabÀ» ÀÌ¿ëÇÏ¿© ½Ã¹Ä·¹À̼ÇÀ» ÇÏ¿´°í, À̸¦ HDL·Î ¼³°èÇÏ°í, µ¿½Ã¿¡ Xilinx»çÀÇ System Generator¸¦ »ç¿ëÇÏ¿© ±¸ÇöÇÏ¿´°í, Timming Analysis¿Í Resource estimationµµ ÇÏ¿´´Ù.
|
¿µ¹®³»¿ë (English Abstract) |
The class of BCH codes is a large class of error correction codes. HDL implementation of BCH code generator to change code rate. and used System Generator, and implemented hardware to FPGA. Loaded bit stream to a FPGA board in order to verify this design to Hardware co-simulation from these results. Also, compared as investigated the maximum action frequency through timing analysis and resource of logic in order to evaluate performance of BCH code generator.
|
Å°¿öµå(Keyword) |
BCH Encoder
System generator
|
ÆÄÀÏ÷ºÎ |
PDF ´Ù¿î·Îµå
|