• Àüü
  • ÀüÀÚ/Àü±â
  • Åë½Å
  • ÄÄÇ»ÅÍ
´Ý±â

»çÀÌÆ®¸Ê

Loading..

Please wait....

±¹³» ³í¹®Áö

Ȩ Ȩ > ¿¬±¸¹®Çå > ±¹³» ³í¹®Áö > Çѱ¹Á¤º¸Åë½ÅÇÐȸ ³í¹®Áö (Journal of the Korea Institute of Information and Communication Engineering)

Çѱ¹Á¤º¸Åë½ÅÇÐȸ ³í¹®Áö (Journal of the Korea Institute of Information and Communication Engineering)

Current Result Document :

ÇѱÛÁ¦¸ñ(Korean Title) UHF RFID ÅÂ±× Ä¨¿ë ÀúÀü·Â EEPROM¼³°è
¿µ¹®Á¦¸ñ(English Title) A Low-power EEPROM design for UHF RFID tag chip
ÀúÀÚ(Author) ÀÌ¿øÀç   ÀÌÀçÇü   ¹Ú°æȯ   ÀÌÁ¤È¯   ÀÓ±ÔÈ£   °­Çü±Ù   °íºÀÁø   ¹Ú¹«ÈÆ   ÇÏÆǺÀ   ±è¿µÈñ   Won-Jae Yi   Jae-Hyung Lee   Kyung-Hwan Park   Jung-Hwan Lee   Gyu-Ho Lim   Hyung-Geun Kang   Bong-Jin Ko   Mu-Hun Park   Pan-Bong Ha   Young-Hee Kim  
¿ø¹®¼ö·Ïó(Citation) VOL 10 NO. 03 PP. 0486 ~ 0495 (2006. 03)
Çѱ۳»¿ë
(Korean Abstract)
º» ³í¹®¿¡¼­ ´Â Ç÷¡½¬ ¼¿À» »ç¿ëÇÏ¿© ¼öµ¿Çü UHF RFID ÅÂ±× Ä¨¿¡ »ç¿ëµÇ´Â ÀúÀü·Â 1Kb µ¿±â½Ä EEPROMÀ» ¼³°èÇÏ¿´´Ù. ÀúÀü·Â EEPROMÀ» ±¸ÇöÇϱâ À§ÇÑ ¹æ¹ýÀ¸·Î ´ÙÀ½°ú °°Àº 4°¡Áö ¹æ¹ýÀ» Á¦¾ÈÇÏ¿´´Ù. ù°, VDD(=1.5V)¿Í VDDP(=2.5V)ÀÇ ÀÌÁß Àü¿ø °ø±ÞÀü¾Ð ¹æ½ÄÀ» »ç¿ëÇÏ¿´°í, µÑ°, µ¿±â½Ä ȸ·Î ¼³°è¿¡¼­ Ŭ·°(clock) ½ÅÈ£°¡ °è¼Ó Ŭ·°Å·(clocking)À¸·Î ÀÎÇÑ ½ºÀ§Äª Àü·ù(switching current)°¡ È帣´Â °ÍÀ» ¸·±â À§ÇØ CKE(Clock Enable) ½ÅÈ£¸¦ »ç¿ëÇÏ¿´´Ù. ¼Â°, Àб⠻çÀÌŬ¿¡¼­ Àü·ù ¼¾½Ì(current sensing) ¹æ½Ä ´ë½Å ÀúÀü·Â ¼Ò¸ð¸¦ °®´Â clocked inverter¸¦ »ç¿ëÇÑ ¼¾½Ì ¹æ½ÄÀ» »ç¿ëÇÏ¿´À¸¸ç, ³Ý°, ¾²±â ¸ðµå½Ã Voltage-up º¯È¯±â(converter) ȸ·Î¸¦ »ç¿ëÇÏ¿© ±âÁØÀü¾Ð ¹ß»ý±â(Reference Voltage Generator)¿¡´Â ÀúÀü¾ÐÀÎ VDD¸¦ »ç¿ëÇÒ ¼ö ÀÖµµ·Ï ÇÏ¿© Àü·Â ¼Ò¸ð¸¦ ÁÙÀÏ ¼ö°¡ ÀÖ¾ú´Ù. 0.25§­ EEPROM °øÁ¤À» ÀÌ¿ëÇÏ¿© ĨÀ» Á¦ÀÛÇÏ¿´À¸¸ç, 1Kb EEPROMÀ» ¼³°èÇÑ °á°ú Àб⠸ðµå¿Í ¾²±â ¸ðµå ½Ã¿¡ ¼Ò¸ðµÇ´Â Àü·ÂÀº °¢°¢ 4.25§Ð¿Í 25§ÐÀÌ°í, ·¹À̾ƿô ¸éÀû(layout area)Àº 646.3 ¡¿ 657.68ÀÌ´Ù.
¿µ¹®³»¿ë
(English Abstract)
In this paper, a low-power 1Kb synchronous EEPROM is designed with flash cells for passive UHF RFID tag chips. To make a low-power EEPROM, four techniques are newly proposed. Firstly, dual power supply voltages VDD(1.5V) and VDDP(2.5V), are used. Secondly, CKE signal is used to remove switching current due to clocking of synchronous circuits. Thirdly, a low-speed but low-power sensing scheme using clocked inverters is used instead of the conventional current sensing method. Lastly, the low-voltage, VDD for the reference voltage generator is supplied by using the Voltage-up converter in write cycle. An EEPROM is fabricated with the 0.25§­ EEPROM process. Simulation results show that power dissipations are 4.25§Ð in the read cycle and 25§Ð in the write cycle, respectively. The layout area is 646.3 ¡¿ 657.68.
Å°¿öµå(Keyword) RFID   EEPROM   Low-power   Sense amplifier  
ÆÄÀÏ÷ºÎ PDF ´Ù¿î·Îµå