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Ȩ Ȩ > ¿¬±¸¹®Çå > ±¹³» ³í¹®Áö > Çѱ¹Á¤º¸Åë½ÅÇÐȸ ³í¹®Áö (Journal of the Korea Institute of Information and Communication Engineering)

Çѱ¹Á¤º¸Åë½ÅÇÐȸ ³í¹®Áö (Journal of the Korea Institute of Information and Communication Engineering)

Current Result Document :

ÇѱÛÁ¦¸ñ(Korean Title) RS(23,17) ¸®µå-¼Ö·Î¸ó º¹È£±â ¼³°è
¿µ¹®Á¦¸ñ(English Title) Design of a RS(23,17) Reed-Solomon Decoder
ÀúÀÚ(Author) °­¼ºÁø   Sung-Jin Kang  
¿ø¹®¼ö·Ïó(Citation) VOL 12 NO. 12 PP. 2286 ~ 2292 (2008. 12)
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(Korean Abstract)
º» ³í¹®¿¡¼­´Â MB-OFDM(Multiband-Orthogonal Frequency Division Multiplexing) ½Ã½ºÅÛ¿¡¼­ »ç¿ëµÇ´Â RS(23,17)ºÎÈ£¿¡ ´ëÇÑ º¹È£±âÀÇ ÃÖÀû ±¸Á¶¸¦ Á¦¾ÈÇÏ°í, ¼³°èÇÏ¿´´Ù. Á¦¾ÈµÈ º¹È£±â ±¸Á¶´Â ÆÄÀÌÇÁ ¶óÀÎ ±¸Á¶¸¦ °®´Â ¼öÁ¤µÈ À¯Å¬¸®µå(Modified Euclidean) ¾Ë°í¸®ÁòÀ» »ç¿ëÇϸç, MB-OFDM ½Ã½ºÅÛ¿¡ ÃÖÀûÈ­µÇ¾î ÀÛÀº º¹È£ Áö¿¬(latency) ¹× Çϵå¿þ¾î º¹Àâµµ¸¦ °¡Áø´Ù. Á¦¾ÈµÈ º¹È£±â´Â Verilog HDLÀ» »ç¿ëÇÏ¿© ±¸ÇöµÇ¾ú°í, »ï¼º 65nm library¸¦ ÀÌ¿ëÇÏ¿© ÇÕ¼ºÇÏ¿´´Ù. 350MHz·Î ÇÕ¼ºÇßÀ» ¶§ timing violationÀÌ ¹ß»ýÇÏÁö ¾Ê¾Ò±â ¶§¹®¿¡, ½ÇÁ¦ ASICÀ» Á¦ÀÛÇصµ 250MHz±îÁö µ¿ÀÛÇϸç, gate count´Â 20,710·Î ³ªÅ¸³µ´Ù.
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(English Abstract)
In this paper, we design a RS(23,17) decoder for MB-OFDM(Multiband-Orthogonal Frequency Division Multiplexing) system, in which Modified Euclidean(ME) algorithm is adopted for key equation solver block. The proposed decoder has been optimized for MB-OFDM system so that it has less latency and hardware complexity. Additionally, we have implemented the proposed decoder using Verilog HDL and synthesized with Samsung 65nm library. From synthesis results, it can operate at clock frequency of 250MHz, and gate count is 20,710.
Å°¿öµå(Keyword) ¸®µå-¼Ö·Î¸ó º¹È£±â   MB-OFDM   ¼öÁ¤µÈ À¯Å¬¸®µå ¾Ë°í¸®Áò   KES  
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