ÇѱÛÁ¦¸ñ(Korean Title) |
PCB Module¿¡¼ÀÇ Processor¿Í DDR2 ¸Þ¸ð¸® »çÀÌ¿¡ ÀÎÅÍÆäÀ̽ºµÇ´Â °í¼Ó½ÅÈ£ Ç°ÁúÈ®º¸¸¦ À§ÇÑ SIÇؼ® |
¿µ¹®Á¦¸ñ(English Title) |
SI Analysis for Quality Assurance of High-Speed Signal Interfaced Between Processor and DDR2 Memory on PCB Module |
ÀúÀÚ(Author) |
ÇÏÇö¼ö
±è¹Î¼º
ÇÏÆǺÀ
±è¿µÈñ
Hyeon-Su Ha
Min-Sung Kim
Pan-Bong Ha
Young-Hee Kim
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¿ø¹®¼ö·Ïó(Citation) |
VOL 17 NO. 02 PP. 0386 ~ 0389 (2013. 10) |
Çѱ۳»¿ë (Korean Abstract) |
º» ³í¹®¿¡¼´Â Processor¿Í DDR2 »çÀÌ¿¡ ÀÎÅÍÆäÀ̽ºµÇ´Â °í¼Ó½ÅÈ£ÀÇ Signal Integrity Çؼ®À» À§ÇØ IC ChipÀÇ IBIS Model°ú Transmission LineÀÇ S-Parameter¸¦ ÀÌ¿ëÇÏ¿© °í¼Ó½ÅÈ£ÀÇ Transient Çؼ®À» ¼öÇàÇÏ°í Eye DiagramÀ» »ý¼ºÇÏ¿´´Ù. °í¼ÓÀ¸·Î µ¿ÀÛÇÏ´Â DQ, DQS/DQSb ½ÅÈ£ ¹× Clock, Address, Control ½ÅÈ£ÀÇ Eye Diagram¿¡¼ Setup/Hold ±¸°£µ¿¾È Timing Margin°ú Voltage MarginÀ» ÃøÁ¤ÇÏ¿´À¸¸ç Over-/Under-shoot ¹× Differential ½ÅÈ£ÀÇ Cross Point°¡ Spec¿¡ ¸¸Á·ÇÏ´ÂÁö È®ÀÎÇÏ¿© ½ÅÈ£ÀÇ Ç°ÁúÀ» È®º¸ÇÏ¿´´Ù.
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¿µ¹®³»¿ë (English Abstract) |
In this paper, for signal integrity analysing high-speed signal between a processor and a DDR2 memory, transient analysis is done and eye diagrams are generated using IBIS models of IC chips and S-parameters of transmission line. From the eye diagrams of such high-speed signals as DQ, DQS/DQSb, Clock, Address and Control, signal quality is assured through measuring timing and voltage margins during setup and hold times and verifying that the over-/under-shoot and the cross points of differential signals satisfy their specifications.
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Å°¿öµå(Keyword) |
SI Analysis
DDR2
High-Speed Signal
PCB Module
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ÆÄÀÏ÷ºÎ |
PDF ´Ù¿î·Îµå
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