Çѱ¹Á¤º¸Åë½ÅÇÐȸ ³í¹®Áö (Journal of the Korea Institute of Information and Communication Engineering)
Current Result Document :
ÇѱÛÁ¦¸ñ(Korean Title) |
¸¶ÀÌÅ©·Î Àü·ÂÀÇ ÃàÂ÷±Ù»çÇü ¾Æ³¯·Î±×-µðÁöÅÐ º¯È¯±â¸¦ À§ÇÑ ½Ã°£ µµ¸ÞÀÎ ºñ±³±â |
¿µ¹®Á¦¸ñ(English Title) |
A Time-Domain Comparator for Micro-Powered Successive Approximation ADC |
ÀúÀÚ(Author) |
¾îÁöÈÆ
±è»óÈÆ
À念Âù
Ji-Hun Eo
Sang-Hun Kim
Young-Chan Jang
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¿ø¹®¼ö·Ïó(Citation) |
VOL 16 NO. 06 PP. 1250 ~ 1259 (2012. 06) |
Çѱ۳»¿ë (Korean Abstract) |
º» ³í¹®¿¡¼´Â ÀúÀü¾Ð °íÇØ»óµµ ÃàÂ÷±Ù»çÇü ¾Æ³¯·Î±×-µðÁöÅÐ º¯È¯±â¸¦ À§ÇÑ ½Ã°£-µµ¸ÞÀÎ ºñ±³±â¸¦ Á¦¾ÈÇÑ´Ù. Á¦¾ÈÇÏ´Â ½Ã°£-µµ¸ÞÀÎ ºñ±³±â´Â Ŭ·° Çǵå-½º·ç º¸»óȸ·Î¸¦ Æ÷ÇÔÇÑ Àü¾ÐÁ¦¾îÁö¿¬ º¯È¯±â, ½Ã°£ ÁõÆø±â, ±×¸®°í ¹ÙÀ̳ʸ® À§»ó °ËÃâ±â·Î ±¸¼ºµÈ´Ù. Á¦¾ÈÇÏ´Â ½Ã°£-µµ¸ÞÀÎ ºñ±³±â´Â ÀÛÀº ÀÔ·Â ºÎÇÏ Ä³ÆнÃÅϽº¸¦ °¡Áö¸ç, Ŭ·° Çǵå-½º·ç ³ëÀÌÁ º¸»óÇÑ´Ù. ½Ã°£-µµ¸ÞÀÎ ºñ±³±âÀÇ Æ¯¼ºÀ» ºÐ¼®Çϱâ À§ÇØ ´Ù¸¥ ½Ã°£-µµ¸ÞÀÎ ºñ±³±â¸¦ °¡Áö´Â µÎ °³ÀÇ 1V 10-bit 200-kS/s ÃàÂ÷±Ù»çÇü ¾Æ³¯·Î±×-µðÁöÅÐ º¯È¯±â°¡ 0.18-¥ìm 1-poly 6-metal CMOS °øÁ¤¿¡¼ ±¸ÇöµÈ´Ù. 11.1 kHzÀÇ ¾Æ³¯·Î±× ÀԷ½ÅÈ£¿¡ ´ëÇØ ÃøÁ¤µÈ SNDRÀº 56.27 dBÀ̸ç, Á¦¾ÈµÈ ½Ã°£-µµ¸ÞÀÎ ºñ±³±âÀÇ Å¬·° Çǵå-½º·ç º¸»óȸ·Î¿Í ½Ã°£ ÁõÆø±â°¡ ¾à 6 dBÀÇ SNDRÀ» Çâ»ó½ÃŲ´Ù. ±¸ÇöµÈ 10-bit 200-kS/s ÃàÂ÷±Ù»çÇü ¾Æ³¯·Î±×-µðÁöÅÐ º¯È¯±âÀÇ Àü·Â¼Ò¸ð¿Í ¸éÀûÀº °¢°¢ 10.39 ¥ìW¿Í 0.126 mm2 ÀÌ´Ù.
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¿µ¹®³»¿ë (English Abstract) |
In this paper, a time-domain comparator is proposed for a successive approximation (SA) analog-to-digital converter (ADC) with a low power and high resolution. The proposed time-domain comparator consists of a voltage-controlled delay converter with a clock feed-through compensation circuit, a time amplifier, and binary phase detector. It has a small input capacitance and compensates the clock feed-through noise. To analyze the performance of the proposed time-domain comparator, two 1V 10-bit 200-kS/s SA ADCs with a different time-domain comparator are implemented by using 0.18-¥ìm 1-poly 6-metal CMOS process. The measured SNDR of the implemented SA ADC is 56.27 dB for the analog input signal of 11.1 kHz, and the clock feed-through compensation circuit and time amplifier of the proposed time-domain comparator enhance the SNDR of about 6 dB. The power consumption and area of the implemented SA ADC are 10.39 ¥ìW and 0.126 mm2, respectively.
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Å°¿öµå(Keyword) |
½Ã°£-µµ¸ÞÀÎ ºñ±³±â
Àü¾ÐÁ¦¾îÁö¿¬ º¯È¯±â
ÃàÂ÷±Ù»çÇü ¾Æ³¯·Î±×-µðÁöÅÐ º¯È¯±â
time-domain comparator
voltage-controlled delay converter
successiveapproximationanalog-to-digital converter
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