Á¤º¸°úÇÐȸ ³í¹®Áö A : ½Ã½ºÅÛ ¹× ÀÌ·Ð
Current Result Document :
ÇѱÛÁ¦¸ñ(Korean Title) |
¸Å´Ï ÄÚ¾î ±â¹Ý ÆÐŶ ÇÁ·Î¼¼¼ µðÀÚÀÎ À̽´ |
¿µ¹®Á¦¸ñ(English Title) |
Design Challenges of Many-core based Packet Processors |
ÀúÀÚ(Author) |
ÀÌÇõÁØ
Hyuk-Jun Lee
|
¿ø¹®¼ö·Ïó(Citation) |
VOL 40 NO. 02 PP. 0068 ~ 0076 (2013. 04) |
Çѱ۳»¿ë (Korean Abstract) |
ÆÐŶ ó¸® ¼ÒÇÁÆ®¿þ¾î¿¡ Á¸ÀçÇÏ´Â º´·Ä¼ºÀº ¸Å´Ï ÄÚ¾î ±â¹Ý ÆÐŶ ÇÁ·Î¼¼¼¸¦ ÅëÇØ ÃÊ´ç ¼ö ¾ï °³ÀÇ ÆÐŶÀÇ Ã³¸®¸¦ °¡´ÉÇÏ°Ô ¸¸µé¾ú´Ù. ±×·¯³ª º¹ÀâÇØÁö´Â ÆÐŶ ó¸® ¼ÒÇÁÆ®¿þ¾î °³¹ß°ú ¼ö ¹é °³ÀÇ ÇÁ·Î¼¼¼ Äھ ÁýÀûÇÑ ¸Å´Ï ÄÚ¾î ±â¹Ý ÆÐŶ ÇÁ·Î¼¼¼ Á¦ÀÛÀº ¸¹Àº »õ·Î¿î ¹®Á¦¸¦ ¾ß±âÇÏ°í ÀÖ´Ù. ÀÌ ³í¹®¿¡¼ ´ç¸éÇÏ°í ÀÖ´Â ¿©·¯ °¡Áö ¹®Á¦µé°ú ÇØ°áÃ¥¿¡ ´ëÇØ ¾Ë¾Æº»´Ù. ù°, ÇöÀç »ç¿ëµÇ°í ÀÖ´Â ÇÁ·Î¼¼¼ ¹è¿ ±¸Á¶¿¡ ´ëÇÏ¿© ¾Ë¾Æº¸°í µÑ°, °¢°¢ÀÇ Äھ ÆÐŶ 󸮸¦ À§ÇØ ½º·¹µå, ¸í·É¾î ÁýÇÕ, ij½¬¸¦ ÃÖÀûÈ ½ÃÅ°´Â ¹æ¹ý¿¡ ´ëÇØ ¾Ë¾Æº»´Ù. ¼Â°, ÆÐŶ ÇÁ·Î¼¼¼¿¡¼´Â ÃÊ´ç ¼ö¹é ±â°¡ ºñÆ®¸¦ ó¸®Çϱâ À§ÇØ QoS¸¦ º¸ÀåÇØ ÁÙ ¼ö ÀÖ´Â °í ´ë¿ªÆøÀÇ ¸Þ¸ð¸® ½Ã½ºÅÛÀÌ ÇÊ¿äÇѵ¥ À̸¦ À§ÇÑ ±¸Á¶¸¦ ¾Ë¾Æº»´Ù. ³Ý°, ÆÐŶ ÇÁ·Î¼¼¼¿¡¼´Â µ¥ÀÌÅ͸¦ ¸¹Àº Äھ °øÀ¯ÇÔ¿¡ µû¶ó ij½¬ ÀÏ°ü¼º(cache coherency) ¹®Á¦¿Í ÀӰ豸¿ª(critical section) ¹®Á¦°¡ ¹ß»ýÇϴµ¥ ÆÐŶ ó¸® °üÁ¡¿¡¼ À̸¦ ÇØ°áÇÏ´Â ¿©·¯ ¹æ½Ä¿¡ ´ëÇØ ¾Ë¾Æº»´Ù. ¸¶Áö¸·À¸·Î ÇöÀç À̽´¿Í ÇÔ²² °¡±î¿î Àå·¡¿¡ ¼ö õ °³ÀÇ Äھ ÁýÀûµÈ ¸Å´Ï ÄÚ¾î Á¦ÀÛ ½Ã ¹ß»ýµÇ´Â ¹®Á¦Á¡¿¡ ´ëÇÏ¿© ¾Ë¾Æº»´Ù. ƯÈ÷ ij½¬ ÀÏ°ü¼º ¹®Á¦¿Í ÀӰ豸¿ª ¹®Á¦¸¦ È®À强 Ãø¸é¿¡¼ ºÐ¼®ÇÏ°í ºñ¿ë Àý¾à Ãø¸é¿¡¼ À̱âÁ¾ ÄÚ¾î »ç¿ë ¹®Á¦¸¦ »ìÆ캻´Ù.
|
¿µ¹®³»¿ë (English Abstract) |
Abundant parallelism in packet processing applications has taken advantage of the many-core processor technology to process hundreds of millions of packets per second. However, integrating hundreds of processor cores and increasing packet processing complexity pose many challenges in designing a many-core based packet processor. In this paper, we discuss design issues and current solutions to exiting problems. First, two processor array architectures are compared. Second, we discuss how to optimize the processor core features such as threading, special instructions, on-chip cache architecture from a packet processing perspective. Third, we discuss a high-performance QoS-aware memory system to process several hundred Gbps multi-class packet stream. Fourth, accessing shared data in the many-core based system could cause a serious performance problem. Various methods to maintain cache coherency and lock the critical section will be discussed. In addition to current issues and solutions, we present future design challenges assuming the process technology continuously scales and software designers add more complexity to the packet processing software. We discuss the scalability of cache coherency protocols and locking methods as the number of cores reaches a few thousands and how to deal with a heterogeneous processor core architecture proposed for a cost reduction.
|
Å°¿öµå(Keyword) |
ÆÐŶ ó¸®
¸Å´ÏÄÚ¾î ÇÁ·Î¼¼¼
ij½¬ ÀÏ°ü¼º
ÀӰ豸¿ª
¸Þ¸ð¸® ´ë¿ªÆø
packet processing
many core processor
cache coherency
critical section
memory bandwidth
|
ÆÄÀÏ÷ºÎ |
PDF ´Ù¿î·Îµå
|