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ÇѱÛÁ¦¸ñ(Korean Title) |
½Ã½ºÅÛ-¿Â-ĨÀÇ Çϵå¿þ¾î-¼ÒÇÁÆ®¿þ¾î ÅëÇÕ ½Ã¹Ä·¹À̼ÇÀ» À§ÇÑ ´Ù¸ñÀû ¼³°è ÇÁ·¹ÀÓ¿öÅ© |
¿µ¹®Á¦¸ñ(English Title) |
A Multipurpose Design Framework for Hardware-Software Cosimulation of System-on-Chip |
ÀúÀÚ(Author) |
ÁÖ¿µÇ¥
À±´ö¿ë
±è¼ºÂù
Çϼøȸ
Young-Pyo Joo
Dukyoung Yun
Sungchan Kim
Soonhoi Ha
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¿ø¹®¼ö·Ïó(Citation) |
VOL 35 NO. 10 PP. 0485 ~ 0496 (2008. 10) |
Çѱ۳»¿ë (Korean Abstract) |
SoC(System-on-Chip)¸¦ ¼³°èÇÔ¿¡ ÀÖ¾î¼ Ä¨ÀÇ º¹Àâµµ Áõ°¡·Î ÀÎÇÏ¿©, RTL(Register Transfer Level)¿¡ ±â¹ÝÇÑ ±âÁ¸ÀÇ ½Ã½ºÅÛ ¼º´É ºÐ¼® ¹× °ËÁõ ±â¹ý ¸¸À¸·Î´Â Á¡Â÷ ª¾ÆÁö´Â ¡®½ÃÀå Àû±â ÃâÇÏ (time-to-market)¡¯ ¿ä±¸¿¡ È¿À²ÀûÀ¸·Î ´ëÀÀÇÒ ¼ö ¾ø°Ô µÇ¾ú´Ù. À̸¦ ±Øº¹Çϱâ À§ÇÏ¿© ¼³°è Ãʱ⠴ܰèºÎÅÍ Áö¼ÓÀûÀ¸·Î ½Ã½ºÅÛÀ» °ËÁõÇϱâ À§ÇÑ »õ·Î¿î ¼³°è ¹æ¹ýÀÌ ¿ä±¸µÇ¾úÀ¸¸ç, TLM(Transaction Level Modeling) Ãß»óÈ ¼öÁØÀ» °¡Áø Çϵå¿þ¾î-¼ÒÇÁÆ®¿þ¾î(HW-SW) ÅëÇÕ ½Ã¹Ä·¹À̼ÇÀÌ ÀÌ·¯ÇÑ ¹®Á¦¸¦ ÇØ°áÇϱâ À§ÇÑ ¹æ¹ýÀ¸·Î ³Î¸® ¿¬±¸µÇ°í ÀÖ´Ù. ±×·¯³ª ´ëºÎºÐÀÇ HW-SW ÅëÇÕ ½Ã¹Ä·¹ÀÌÅ͵éÀº ´Ù¾çÇÑ Ãß»óÈ ¼öÁØ Áß ÀϺθ¸À» Áö¿øÇÏ°í ÀÖÀ¸¸ç, ¼·Î ´Ù¸¥ Ãß»óÈ ¼öÁØÀ» Áö¿øÇÏ´Â Åøµé °£ÀÇ ¿¬°èµµ ½±Áö ¾Ê´Ù. À̸¦ ±Øº¹Çϱâ À§ÇÏ¿© º» ³í¹®¿¡¼´Â HW-SW ÅëÇÕ ½Ã¹Ä·¹À̼ÇÀ» À§ÇÑ ´Ù¸ñÀû ¼³°è ÇÁ·¹ÀÓ¿öÅ©¸¦ Á¦¾ÈÇÑ´Ù. Á¦¾ÈÇÏ´Â ÇÁ·¹ÀÓ¿öÅ©´Â ¼ÒÇÁÆ®¿þ¾î ÀÀ¿ëÀÇ ¼³°è¸¦ Æ÷ÇÔÇϴ ü°èÀûÀÎ SoC ¼³°è Ç÷ο츦 Á¦°øÇϸç, °¢ ¼³°è ´Ü°è¿¡¼ ´Ù¾çÇÑ ±â¹ýµéÀ» À¯¿¬ÇÏ°Ô Àû¿ëÇÒ ¼ö ÀÖ´Â µ¿½Ã¿¡, ´Ù¾çÇÑ HW-SW ÅëÇÕ ½Ã¹Ä·¹ÀÌÅ͵éÀ» Áö¿øÇÑ´Ù. ¶ÇÇÑ Ç÷§ÆûÀ» Ãß»óÈ ¼öÁØ°ú ¸ðµ¨¸µ ¾ð¾î¿¡ µ¶¸³ÀûÀ¸·Î ¼³°èÇÒ ¼ö ÀÖ¾î, ´Ù¾çÇÑ ¼öÁØÀÇ ½Ã¹Ä·¹ÀÌ¼Ç ¸ðµ¨ »ý¼ºÀÌ °¡´ÉÇÏ´Ù. º» ³í¹®¿¡¼´Â ½ÇÇèÀ» ÅëÇÏ¿©, Á¦¾ÈÇÏ´Â ÇÁ·¹ÀÓ¿öÅ©°¡ ARM9 ±â¹ÝÀÇ »ó¿ë SoC Ç÷§ÆûÀ» Á¤È®ÇÏ°Ô ¸ðµ¨¸µ ÇÒ ¼ö ÀÖ´Â µ¿½Ã¿¡, MJPEG ¿¹Á¦ÀÇ ¼º´ÉÀ» 44%±îÁö Çâ»ó½ÃÅ°´Â ¼º´É ÃÖÀûȸ¦ ¼öÇàÇÒ ¼ö ÀÖÀ½À» °ËÁõÇÏ¿´´Ù.
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¿µ¹®³»¿ë (English Abstract) |
As the complexity of SoC (System-on-Chip) design increases dramatically, traditional system performance analysis and verification methods based on RTL (Register Transfer Level) are no more valid for increasing time-to-market pressure. Therefore a new design methodology is desperately required for system verification in early design stages, and hardware-software (HW-SW) cosimulation at TLM (Transaction Level Modeling) level has been researched widely for solving this problem. However, most of HW-SW cosimulators support few restricted abstraction levels only, which makes it difficult to integrate HW-SW cosimulators with different abstraction levels. To overcome this difficulty, this paper proposes a multipurpose framework for HW-SW cosimulation to provide systematic SoC design flow starting from software application design. It supports various design techniques flexibly for each design step, and various HW-SW cosimulators. Since a platform design is possible independently of abstraction levels and description languages, it allows us to generate simulation models with various abstraction levels. We verified the proposed framework to model a commercial SoC platform based on an ARM9 processor. It was also proved that this framework could be used for the performance optimization of an MJPEG example up to 44% successfully.
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Å°¿öµå(Keyword) |
½Ã½ºÅÛ-¿Â-Ĩ
Çϵå¿þ¾î-¼ÒÇÁÆ®¿þ¾î ÅëÇÕ ½Ã¹Ä·¹À̼Ç
ÀÓº£µðµå ½Ã½ºÅÛ
¼³°è Ç÷οì
System-on-Chip
Hardware-software cosimulation
Embedded system
Design flow
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