2011³â Ãá°èÇмú´ëȸ
Current Result Document :
ÇѱÛÁ¦¸ñ(Korean Title) |
A 1.8V 50-MS/s 10-bit 0.18-um CMOS Pipelined ADC without SHA |
¿µ¹®Á¦¸ñ(English Title) |
A 1.8V 50-MS/s 10-bit 0.18-um CMOS Pipelined ADC without SHA |
ÀúÀÚ(Author) |
¾îÁöÈÆ
±è¿ø¸í
±è»óÈÆ
À念Âù
Ji-Hun Uh
Won-Myoung Kim
Sang-Hun Kim
Young-Chan Jang
|
¿ø¹®¼ö·Ïó(Citation) |
VOL 15 NO. 01 PP. 0143 ~ 0146 (2011. 05) |
Çѱ۳»¿ë (Korean Abstract) |
º» ³í¹®Àº 1.2Vpp differential ÀÔ·Â ¹üÀ§¸¦ °¡Áö´Â 50-MS/s 10-bit pipelined ADC¸¦ ¼Ò°³ÇÑ´Ù. ¼³°èµÈ pipelined ADC´Â 8´ÜÀÇ 1.5bit/stage, 1´ÜÀÇ 2bit/stage¿Í digital correction ºí·Ï, bias circuit ¹× reference driver, ±×¸®°í clock generator·Î ±¸¼ºµÈ´Ù. 1.5bit/stage´Â sub-ADC, DAC, gain stage·Î ±¸¼ºµÈ´Ù. ƯÈ÷, ¼³°èµÈ pipelined ADC¿¡¼´Â hardware¿Í power consumptionÀ» ÁÙÀ̱â À§ÇØ SHA¸¦ Á¦°ÅÇÏ¿´À¸¸ç, Àüü ADCÀÇ synamic performance¸¦ Çâ»ó½ÃÅ°±â À§ÇØ linearity°¡ °³¼±µÈ bootstrapped switch¸¦ »ç¿ëÇÏ¿´´Ù. Sub-ADC¸¦ À§ÇÑ reference Àü¾ÐÀº ¿ÜºÎ¿¡¼ Àΰ¡ÇÏÁö ¾Ê°í on-chip reference driver¿¡¼ ¹ß»ý½ÃŲ´Ù. Á¦¾ÈµÈ pipelined ADC´Â 1.8V supply, 0.18um 1-poly 5-metal CMOS °øÁ¤¿¡¼ ¼³°èµÇ¾úÀ¸¸ç, power decoupling capacitor¸¦ Æ÷ÇÔÇÏ¿© 0.95mm^2ÀÇ Ä¨ ¸éÀûÀ» °¡Áø´Ù. ¶ÇÇÑ 60mWÀÇ Àü·Â¼Ò¸ð¸¦ °¡Áø´Ù. ¶ÇÇÑ, Nyquist sampling rate¿¡¼ 9.3-bitÀÇ ENOB¸¦ ³ªÅ¸³»¾ú´Ù.
|
¿µ¹®³»¿ë (English Abstract) |
A 50-MS/s 10-bit pipelined ADC with 1.2Vpp differential input range is proposed in this paper. The designed pipelined ADC consists of eight stage of 1.5bit/stage, one stage of 2bit/stage, digital error correction block, bias & reference driver, and clock generator. 1.5bit/stage is consists of sub-ADC, DAC and gain stage, Specially, a sample-and hold amplifier (SHA) is removed in the designed pipelined ADC to reduce the hardware and power consumption. Also, the proposed bootstrapped switch improves the Linearity of the input analog switch and the dynamic performance of the total ADC. The reference voltage was driven by using the on-chip reference driver without external reference. The proposed pipelined ADC was designed by using a 0.18um 1-poly 5-metal CMOS process with 1.8V supply. The total area including the power decoupling capacitor and power consumption are tex:\small\textstyle$0.95mm^2$ and 60mW, respectively. Also, the simulation result shows the ENOB of 9.3-bit at the Nyquist sampling rate.
|
Å°¿öµå(Keyword) |
ADC
pipeline
bootstrapped switch
reference-driver
|
ÆÄÀÏ÷ºÎ |
PDF ´Ù¿î·Îµå
|