2011³â Ãß°è Çмú´ëȸ
Current Result Document :
ÇѱÛÁ¦¸ñ(Korean Title) |
FPGA¸¦ ÀÌ¿ëÇÑ NCC±â¹ÝÀÇ ½Ç½Ã°£ ½ºÅ×·¹¿À ¸ÅĪ ÇÁ·Î¼¼¼ ±¸Çö |
¿µ¹®Á¦¸ñ(English Title) |
FPGA implementation of NCC-based real-time stereo matching processor |
ÀúÀÚ(Author) |
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Byeong-Jin Kim
Sang-Min Bae
Kwang-Sik Koh
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¿ø¹®¼ö·Ïó(Citation) |
VOL 18 NO. 02 PP. 0322 ~ 0325 (2011. 11) |
Çѱ۳»¿ë (Korean Abstract) |
½ºÅ×·¹¿À ºñÀü ½Ã½ºÅÛ¿¡¼ ÀüÅëÀûÀÎ ¸ÅĪ ¾Ë°í¸®ÁòÀ¸·Î SAD(Sum of Absolute Differences), SSD(Sum of Squared Differences), NCC(Normalized Cross Correlation) µî ´Ù¾çÇÑ ¾Ë°í¸®ÁòÀÌ Á¸ÀçÇÑ´Ù. ±×·¯³ª Çϵå¿þ¾î·Î ½Ç½Ã°£ 󸮸¦ À§ÇÑ ½Ã½ºÅÛÀ» ±¸ÇöÇϱâ À§Çؼ´Â ¸®¼Ò½º°¡ ÇÑÁ¤ µÇ¾îÀÖ´Ù´Â Á¦¾à ¶§¹®¿¡ ¸¹Àº ¿¬±¸¿¡¼ SAD ȤÀº RT(Rank Transform), CT(Census Transform)¸¦ ¸¹ÀÌ »ç¿ëÇÏ°Ô µÈ´Ù. FPGA ³»ºÎ¿¡´Â BRAM(Block RAM)°ú MAC(multiply-accumulator)ÀÎ DSP½½¶óÀ̽º°¡ ÀÌ¹Ì Á¸ÀçÇÑ´Ù. º» ³í¹®¿¡¼´Â BRAM°ú DSP·ÎÁ÷À» È°¿ëÇؼ ÀüÅëÀûÀÎ ¸ÅĪ ¾Ë°í¸®Áò Áß¿¡¼ ¿¬»ê±â »ç¿ëÀÌ °¡Àå ¸¹Àº NCC¸¦ FPGA·Î ½Ç½Ã°£ ó¸® °¡´ÉÇÑ Çϵå¿þ¾î ±¸Á¶¸¦ Á¦¾ÈÇÑ´Ù. |
¿µ¹®³»¿ë (English Abstract) |
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Å°¿öµå(Keyword) |
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