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Çмú´ëȸ ÇÁ·Î½Ãµù

Ȩ Ȩ > ¿¬±¸¹®Çå > Çмú´ëȸ ÇÁ·Î½Ãµù > Çѱ¹Á¤º¸Ã³¸®ÇÐȸ Çмú´ëȸ > 2011³â Ãß°è Çмú´ëȸ

2011³â Ãß°è Çмú´ëȸ

Current Result Document :

ÇѱÛÁ¦¸ñ(Korean Title) FPGA¸¦ ÀÌ¿ëÇÑ NCC±â¹ÝÀÇ ½Ç½Ã°£ ½ºÅ×·¹¿À ¸ÅĪ ÇÁ·Î¼¼¼­ ±¸Çö
¿µ¹®Á¦¸ñ(English Title) FPGA implementation of NCC-based real-time stereo matching processor
ÀúÀÚ(Author) ±èº´Áø   ¹è»ó¹Î   °í±¤½Ä   Byeong-Jin Kim   Sang-Min Bae   Kwang-Sik Koh  
¿ø¹®¼ö·Ïó(Citation) VOL 18 NO. 02 PP. 0322 ~ 0325 (2011. 11)
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(Korean Abstract)
½ºÅ×·¹¿À ºñÀü ½Ã½ºÅÛ¿¡¼­ ÀüÅëÀûÀΠ¸ÅĪ ¾Ë°í¸®ÁòÀ¸·Î SAD(Sum of Absolute Differences), SSD(Sum of Squared Differences), NCC(Normalized Cross Correlation) µî ´Ù¾çÇÑ ¾Ë°í¸®ÁòÀÌ Á¸ÀçÇÑ´Ù. ±×·¯³ª Çϵå¿þ¾î·Î ½Ç½Ã°£ Ã³¸®¸¦ À§ÇÑ ½Ã½ºÅÛÀ» ±¸ÇöÇϱâ À§Çؼ­´Â ¸®¼Ò½º°¡ ÇÑÁ¤ µÇ¾îÀִٴ Á¦¾à ¶§¹®¿¡ ¸¹Àº ¿¬±¸¿¡¼­ SAD È¤Àº RT(Rank Transform), CT(Census Transform)¸¦ ¸¹ÀÌ »ç¿ëÇÏ°Ô µÈ´Ù. FPGA ³»ºÎ¿¡´Â BRAM(Block RAM)°ú MAC(multiply-accumulator)ÀΠDSP½½¶óÀ̽º°¡ À̹̠Á¸ÀçÇÑ´Ù. º» ³í¹®¿¡¼­´Â BRAM°ú DSP·ÎÁ÷À» È°¿ëÇؼ­ ÀüÅëÀûÀΠ¸ÅĪ ¾Ë°í¸®Áò Áß¿¡¼­ ¿¬»ê±â »ç¿ëÀÌ °¡Àå ¸¹Àº NCC¸¦ FPGA·Î ½Ç½Ã°£ Ã³¸® °¡´ÉÇÑ Çϵå¿þ¾î ±¸Á¶¸¦ Á¦¾ÈÇÑ´Ù.
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(English Abstract)
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