2003³â Ãß°è Çмú´ëȸ
Current Result Document : 3 / 3
ÇѱÛÁ¦¸ñ(Korean Title) |
128ºñÆ® ºí·Ï ¾ÏÈ£ ¾Ë°í¸®Áò SEED¿Í UARTÀÇ Àúºñ¿ë FPGA¸¦ ÀÌ¿ëÇÑ ÅëÇÕ ¼³°è ¹× ±¸Çö |
¿µ¹®Á¦¸ñ(English Title) |
An Integrated Design and Implementation of 128-bit block cipher SEED and UART with a low-cost FPGA |
ÀúÀÚ(Author) |
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¿ø¹®¼ö·Ïó(Citation) |
VOL 30 NO. 2-1 PP. 0205 ~ 0207 (2003. 10) |
Çѱ۳»¿ë (Korean Abstract) |
º» ³í¹®¿¡¼´Â ±¹³» Ç¥ÁØ 128ºñÆ® ºí·Ï ¾ÏÈ£È ¾Ë°í¸®ÁòÀÎ SEED¿Í UART¸¦ ÅëÇÕÇÏ¿© ÃÖÀú°¡ÀÇ FPGA·Î ±¸ÇöÇÏ´Â ¹æ¹ýÀ» Á¦¾ÈÇÑ´Ù. ³í¹®[1]¿¡¼ ±¸ÇöÇÑ ¸éÀû ¿ä±¸·®ÀÌ ÃÖ¼Ò·Î ±¸ÇöµÈ SEED ¾ÏÈ£È ¸ðµâÀÇ À¯¿ë¼ºÀ» ½ÇÁ¦ ³»ÀåÇü ½Ã½ºÅÛ¿¡ Àû¿ëÇÏ¿© ±× ½ÇÈ¿¼ºÀ» º¸¿©ÁÖ´Â °ÍÀÌ º» ³í¹®ÀÇ ¸ñÀûÀÌ´Ù. ¿ì¸®°¡ ±¸ÇöÇÑ È¸·Î´Â SEED¸¦ ÅëÇØ ¾Ïȣȸ¦ ÇÑ ÈÄ UART¸¦ ÀÌ¿ëÇÏ¿© ¿ÜºÎ¿ÍÀÇ Åë½ÅÇÒ ¼öµµ ÀÖ°í, SEED¸¦ °Ç³Ê¶Ù°í UART ´Üµ¶¸¸ ÀÌ¿ëÇÏ¿© ¿ÜºÎ¿Í Åë½ÅÀ» ÇÒ ¼öµµ ÀÖ´Ù. ¶ÇÇÑ, SEED ÀÚü¸¦ coprocessor·Î ÀÌ¿ëÇÏ¿© ¾ÏÈ£È/º¹È£È °¡´É¸¸ »ç¿ëÇÒ ¼öµµ ÀÖµµ·Ï ¼³°èÇÏ¿´´Ù. ±¸Çö °á°ú, 10¸¸ °ÔÀÌÆ®¸¦ °®´Â Xilinx »çÀÇ Spartan-II °è¿ÀÇ xc2s100 ½Ã¸®Áî ĨÀ» »ç¿ëÇÏ¿´À» ¶§, SEED¿Í UART¿Í ÁÖº¯ ³í¸® ȸ·Î¸¦ ÇÕÇÏ¿© 84% ÀÌÇÏÀÇ ¸éÀûÀ» Â÷Áö ÇÏ¿´°í, ÃÖ´ë 41.3Mhz Ŭ·°¿¡¼ µ¿ÀÛÇÏ¿´À¸¸ç, SEEDÀÇ ¾ÏÈ£È Ã³¸® ThrougputÀº 54.55Mbps·Î¼ UART¸¦ ÀÌ¿ëÇÏ¿© Åë½ÅÇϴµ¥ ÀüÇô ¹®Á¦°¡ ¾ø¾ú´Ù. |
¿µ¹®³»¿ë (English Abstract) |
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Å°¿öµå(Keyword) |
ºí·Ï ¾ÏÈ£ ¾Ë°í¸®Áò
SEED
UART
FPGA
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ÆÄÀÏ÷ºÎ |
PDF ´Ù¿î·Îµå
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