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| 한글제목(Korean Title) |
A Design of 8 Bits 200KS/s Synchronous SAR ADC |
| 영문제목(English Title) |
A Design of 8 Bits 200KS/s Synchronous SAR ADC |
| 저자(Author) |
김동진
이강윤
Dongjin Kim
Kang-Yoon Lee
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| 원문수록처(Citation) |
VOL 45 NO. 01 PP. 1854 ~ 1855 (2022. 06) |
한글내용
(Korean Abstract) |
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영문내용
(English Abstract) |
This paper presents a design of low power 8 bit 200KS/s Synchronous Successive Approximation Register analog to digital (SAR ADC) converter. The structure consists of Input Buffer, Dynamic Latch Comparator, Capacitive DAC, Reference Voltage Generator, and SAR Logic. The structure is designed using 55-nm Complementary Metal-Oxided-Semiconductor (CMOS) process technology with 1V of supply voltage and 781.2 Hz of input frequency. The results of SAR ADC are achieved an effective number of bits (ENOB) of 7.9 bits and a signal to noise, distortion ration (SNDR) level of 49.9 dB with sampling rate 200KS/s. Furthermore, total power consumption of the structure is 245 uW.
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