JICCE (한국정보통신학회)
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| 한글제목(Korean Title) |
General SPICE Modeling Procedure for Double-Gate Tunnel Field-Effect Transistors |
| 영문제목(English Title) |
General SPICE Modeling Procedure for Double-Gate Tunnel Field-Effect Transistors |
| 저자(Author) |
Syed Faraz
Michael Loong Peng Tan
Yun Seop Yu
|
| 원문수록처(Citation) |
VOL 14 NO. 02 PP. 0115 ~ 0121 (2016. 06) |
한글내용
(Korean Abstract) |
|
영문내용
(English Abstract) |
Currently there is a lack of literature on SPICE-level models of double-gate (DG) tunnel field-effect transistors (TFETs). A DG TFET compact model is presented in this work that is used to develop a SPICE model for DG TFETs implemented with Verilog-A language. The compact modeling approach presented in this work integrates several issues in previously published compact models including ambiguity about the use of tunneling parameters Ak and Bk, and the use of a universal equation for calculating the surface potential of DG TFETs in all regimes of operation to deliver a general SPICE modeling procedure for DG TFETs. The SPICE model of DG TFET captures the drain current-gate voltage (Ids-Vgs) characteristics of DG TFET reasonably well and offers a definite computational advantage over TCAD. The general SPICE modeling procedure presented here could be used to develop SPICE models for any combination of structural parameters of DG TFETs. |
| 키워드(Keyword) |
Compact model
Drain current
Inverter
Potential profile
TFET
Verilog
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| 파일첨부 |
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