JICCE (한국정보통신학회)
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| 한글제목(Korean Title) |
Device Coupling Effects of Monolithic 3D Inverters |
| 영문제목(English Title) |
Device Coupling Effects of Monolithic 3D Inverters |
| 저자(Author) |
Yun Seop Yu
Sung Kyu Lim
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| 원문수록처(Citation) |
VOL 14 NO. 01 PP. 0040 ~ 0044 (2016. 03) |
한글내용
(Korean Abstract) |
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영문내용
(English Abstract) |
The device coupling between the stacked top/bottom field-effect transistors (FETs) in two types of monolithic 3D inverter (M3INV) with/without a metal layer in the bottom tier is investigated, and then the regime of the thickness TILD and dielectric constant r of the inter-layer distance (ILD), the doping concentration Nd (Na), and length Lg of the channel, and the side-wall length L_sw where the stacked FETs are coupled are studied. When N_d(N_a) < 10^16 cm^-3 and L_sw < 20 nm, the threshold voltage shift of the top FET varies almost constantly by the gate voltage of the bottom FET, but when N_d(N_a) > 10^16 cm^-3 or L_sw > 20 nm, the shift decreases and increases, respectively. M3INVs with T_ILD ≥ 50 nm and ε_r ≤ 3.9 can neglect the interaction between the stacked FETs, but when T_ILD or r do not meet the above conditions, the interaction must be taken into consideration.
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| 키워드(Keyword) |
3D integrated circuit (3D IC)
Coupling
Monolithic 3D IC
Parasitic extraction
Threshold voltage
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| 파일첨부 |
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