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Çѱ¹Á¤º¸Åë½ÅÇÐȸ ³í¹®Áö (Journal of the Korea Institute of Information and Communication Engineering)
Çѱ¹Á¤º¸Åë½ÅÇÐȸ ³í¹®Áö (Journal of the Korea Institute of Information and Communication Engineering)
Current Result Document :
2
/ 2
ÀÌÀü°Ç
ÇѱÛÁ¦¸ñ(Korean Title)
IoT º¸¾È ÀÀ¿ëÀ» À§ÇÑ °æ·® ºí·Ï ¾ÏÈ£ CLEFIAÀÇ È¿À²ÀûÀÎ Çϵå¿þ¾î ±¸Çö
¿µ¹®Á¦¸ñ(English Title)
An Efficient Hardware Implementation of Lightweight Block Cipher Algorithm CLEFIA for IoT Security Applications
ÀúÀÚ(Author)
¹è±âö
½Å°æ¿í
Gi-chur Bae
Kyung-wook Shin
¿ø¹®¼ö·Ïó(Citation)
VOL 20 NO. 02 PP. 0351 ~ 0358 (2016. 02)
Çѱ۳»¿ë
(Korean Abstract)
°æ·® ºí·Ï ¾ÏÈ£ ¾Ë°í¸®Áò CLEFIAÀÇ È¿À²ÀûÀÎ Çϵå¿þ¾î ¼³°è¿¡ ´ëÇÏ¿© ±â¼úÇÑ´Ù. ¼³°èµÈ CLEFIA º¸¾È ÇÁ·Î¼¼¼´Â 128/192/256-ºñÆ®ÀÇ ¼¼ °¡Áö ¸¶½ºÅÍÅ° ±æÀ̸¦ Áö¿øÇϸç, º¯ÇüµÈ GFN(Generalized Feistel Network) ±¸Á¶¸¦ ±â¹ÝÀ¸·Î 8-ºñÆ® µ¥ÀÌÅÍ Æнº·Î ±¸ÇöµÇ¾ú´Ù. ¶ó¿îµåÅ° »ý¼ºÀ» À§ÇÑ Áß°£Å° °è»ê¿ë GFN°ú ¾ÏÈ£‧º¹È£ ¶ó¿îµå º¯È¯¿ë GFNÀ» ´ÜÀÏ µ¥ÀÌÅÍ ÇÁ·Î¼¼½Ì ºí·ÏÀ¸·Î ±¸ÇöÇÏ¿© Çϵå¿þ¾î º¹Àâµµ¸¦ ÃÖ¼ÒÈÇÏ¿´´Ù. º» ³í¹®ÀÇ GFN ºí·ÏÀº ¶ó¿îµå º¯È¯°ú 128-ºñÆ®ÀÇ Áß°£ ¶ó¿îµåÅ° °è»êÀ» À§ÇÑ 4-ºê·£Ä¡ GFN°ú 256-ºñÆ®ÀÇ Áß°£ ¶ó¿îµåÅ° °è»êÀ» À§ÇÑ 8-ºê·£Ä¡ GFNÀ¸·Î À籸¼ºµÇ¾î µ¿ÀÛÇϵµ·Ï ¼³°èµÇ¾ú´Ù. Verilog HDL·Î ¼³°èµÈ CLEFIA º¸¾È ÇÁ·Î¼¼¼¸¦ FPGA·Î ±¸ÇöÇÏ¿© Á¤»ó µ¿ÀÛÇÔÀ» È®ÀÎÇÏ¿´´Ù. Vertex5 XC5VSX50T FPGA¿¡¼ ÃÖ´ë 112 MHz Ŭ·ÏÀ¸·Î µ¿ÀÛ °¡´ÉÇϸç, ¸¶½ºÅÍÅ° ±æÀÌ¿¡ µû¶ó 81.5 ~ 60 MbpsÀÇ ¼º´ÉÀ» °®´Â °ÍÀ¸·Î Æò°¡µÇ¾ú´Ù.
¿µ¹®³»¿ë
(English Abstract)
This paper describes an efficient hardware implementation of lightweight block cipher algorithm CLEFIA. The CLEFIA crypto-processor supports for three master key lengths of 128/192/256-bit, and it is based on the modified generalized Feistel network (GFN). To minimize hardware complexity, a unified processing unit with 8 bits data-path is designed for implementing GFN that computes intermediate keys to be used in round key scheduling, as well as carries out round transformation. The GFN block in our design is reconfigured not only for performing 4-branch GFN used for round transformation and intermediate round key generation of 128-bit, but also for performing 8-branch GFN used for intermediate round key generation of 256-bit. The CLEFIA crypto-processor designed in Verilog HDL was verified by using Virtex5 XC5VSX50T FPGA device. The estimated throughput is 81.5 ~ 60 Mbps with 112 MHz clock frequency.
Å°¿öµå(Keyword)
CLEFIA
°æ·® ºí·Ï ¾ÏÈ£
Á¤º¸º¸¾È
IoT º¸¾È
ºñ¹ÐÅ° ¾ÏÈ£
CLEFIA
lightweight block cipher
information security
IoT security
secret key cryptography
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