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Ȩ Ȩ > ¿¬±¸¹®Çå > ±¹³» ³í¹®Áö > Çѱ¹Á¤º¸Åë½ÅÇÐȸ ³í¹®Áö (Journal of the Korea Institute of Information and Communication Engineering)

Çѱ¹Á¤º¸Åë½ÅÇÐȸ ³í¹®Áö (Journal of the Korea Institute of Information and Communication Engineering)

Current Result Document : 68 / 272 ÀÌÀü°Ç ÀÌÀü°Ç   ´ÙÀ½°Ç ´ÙÀ½°Ç

ÇѱÛÁ¦¸ñ(Korean Title) °í¼º´É HEVC ºÎÈ£±â¸¦ À§ÇÑ ·çÇÁ ³» ÇÊÅÍ Çϵå¿þ¾î ¼³°è
¿µ¹®Á¦¸ñ(English Title) Hardware Design of In-loop Filter for High Performance HEVC Encoder
ÀúÀÚ(Author) ¹Ú½Â¿ë   ÀÓÁؼº   ·ù±¤±â   Seungyong Park   Junseong Im   Kwangki Ryoo  
¿ø¹®¼ö·Ïó(Citation) VOL 20 NO. 02 PP. 0335 ~ 0342 (2016. 02)
Çѱ۳»¿ë
(Korean Abstract)
º» ³í¹®¿¡¼­´Â °í¼º´É HEVC(High Efficiency Video Coding) ºÎÈ£±â¸¦ À§ÇÑ ·çÇÁ ³» ÇÊÅÍÀÇ È¿À²ÀûÀÎ Çϵå¿þ¾î ±¸Á¶¸¦ Á¦¾ÈÇÑ´Ù. HEVC´Â ¾çÀÚÈ­ ¿¡·¯°¡ ¹ß»ýÇÏ´Â º¹¿ø ¿µ»ó¿¡¼­ È­ÁúÀ» Çâ»ó½ÃÅ°±â À§ÇØ µðºí·ÏÅ· ÇÊÅÍ¿Í SAO(Sample Adaptive Offset)À¸·Î ±¸¼ºµÈ ·çÇÁ ³» ÇÊÅ͸¦ »ç¿ëÇÑ´Ù. ±×·¯³ª ·çÇÁ ³» ÇÊÅÍ´Â Ãß°¡ÀûÀÎ ¿¬»êÀ¸·Î ÀÎÇÏ¿© ºÎÈ£±â¿Í º¹È£±âÀÇ º¹Àâµµ°¡ Áõ°¡µÇ´Â ¿øÀÎÀÌ µÈ´Ù. Á¦¾ÈÇÏ´Â ·çÇÁ ³» ÇÊÅÍ Çϵå¿þ¾î ±¸Á¶´Â ¼öÇà »çÀÌŬ °¨¼Ò¸¦ À§ÇØ µðºí·ÏÅ· ÇÊÅÍ¿Í SAO¸¦ 3´Ü ÆÄÀÌÇÁ¶óÀÎÀ¸·Î ±¸ÇöµÇ¾ú´Ù. ¶ÇÇÑ Á¦¾ÈÇÏ´Â µðºí·ÏÅ· ÇÊÅÍ´Â 6´Ü ÆÄÀÌÇÁ¶óÀÎ ±¸Á¶·Î ±¸ÇöµÇ¾úÀ¸¸ç, È¿À²ÀûÀÎ ÂüÁ¶ ¸Þ¸ð¸® ±¸Á¶¸¦ À§ÇØ »õ·Î¿î ÇÊÅ͸µ ¼ø¼­·Î ¼öÇàµÈ´Ù. Á¦¾ÈÇÏ´Â SAO´Â È­¼ÒµéÀÇ Ã³¸®¸¦ °£¼ÒÈ­ÇÏ¸ç ¼öÇà »çÀÌŬÀ» °¨¼Ò½ÃÅ°±â À§ÇØ Çѹø¿¡ 6°³ÀÇ È­¼Ò¸¦ º´·Ä 󸮵ȴÙ. Á¦¾ÈÇÏ´Â ·çÇÁ ³» ÇÊÅÍ Çϵå¿þ¾î ±¸Á¶´Â Verilog HDL·Î ¼³°èµÇ¾úÀ¸¸ç, TSMC 0.13¥ìm CMOS Ç¥ÁØ ¼¿ ¶óÀ̺귯¸®¸¦ »ç¿ëÇÏ¿© ÇÕ¼ºÇÑ °á°ú ¾à 131K°³ÀÇ °ÔÀÌÆ®·Î ±¸ÇöµÇ¾ú´Ù. ¶ÇÇÑ 164MHzÀÇ µ¿ÀÛ ÁÖÆļö¿¡¼­ 4K@60fpsÀÇ ½Ç½Ã°£ 󸮰¡ °¡´ÉÇϸç, ÃÖ´ë µ¿ÀÛ ÁÖÆļö´Â 416MHzÀÌ´Ù.
¿µ¹®³»¿ë
(English Abstract)
This paper proposes efficient hardware structure of in-loop filter for a high-performance HEVC (High Efficiency Video Coding) encoder. HEVC uses in-loop filter consisting of deblocking filter and SAO (Sample Adaptive Offset) to improve the picture quality in a reconstructed image due to a quantization error. However, in-loop filter causes an increase in complexity due to the additional encoder and decoder operations. A proposed in-loop filter is implemented as a three-stage pipeline to perform the deblocking filtering and SAO operation with a reduced number of cycles. The proposed deblocking filter is also implemented as a six-stage pipeline to improve efficiency and performs a new filtering order for efficient memory architecture. The proposed SAO processes six pixels parallelly at a time to reduce execution cycles. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 131K logic gates in TSMC 0.13¥ìm process. At 164MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 60fps in real time.
Å°¿öµå(Keyword) HEVC ºÎÈ£±â   ·çÇÁ ³» ÇÊÅÍ   µðºí·ÏÅ· ÇÊÅÍ   SAO(ÀûÀÀÀû »ùÇà ¿ÀÇÁ¼Â)   Çϵå¿þ¾î ¼³°è   HEVC Encoder   In-loop Filter   Deblocking Filter   SAO(Sample Adaptive Offset)   Hardware Design  
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