Çѱ¹Á¤º¸Åë½ÅÇÐȸ ³í¹®Áö (Journal of the Korea Institute of Information and Communication Engineering)
Current Result Document :
ÇѱÛÁ¦¸ñ(Korean Title) |
SPI-4.2 ÀÎÅÍÆäÀ̽º ÄÚ¾îÀÇ ¼³°è |
¿µ¹®Á¦¸ñ(English Title) |
A Design of SPI-4.2 Interface Core |
ÀúÀÚ(Author) |
¼Õ½ÂÀÏ
Seung-Il Sonh
|
¿ø¹®¼ö·Ïó(Citation) |
VOL 08 NO. 06 PP. 1107 ~ 1114 (2004. 10) |
Çѱ۳»¿ë (Korean Abstract) |
½Ã½ºÅÛ ÆÐŶ ÀÎÅÍÆäÀ̽º 4·¹º§ 2´Ü°è(System Packet Interface Leve14 Phase 2)´Â 10Gbps ÀÌ´õ³ÝÀÀ¿ë »Ó¸¸ ¾Æ´Ï¶ó, OC-192 ´ë¿ªÆøÀÇ ATM ¹× POS¸¦ ÅëÇÑ ÆÐŶ ¶Ç´Â ¼¿ Àü¼ÛÀ» À§ÇÑ ¹°¸®°èÃþ°ú ¸µÅ©°èÃþ ¼ÒÀÚ°£ÀÇ ÀÎÅÍÆäÀ̽ºÀÌ´Ù.
SPI-4.2 ÄÚ¾î´Â Àü¼Û ÀÎÅÍÆäÀ̽º ºí·Ï°ú ¼ö½Å ÀÎÅÍÆäÀ̽º ºí·ÏÀ¸·Î ±¸¼ºµÇ¾î ÀÖÀ¸¸ç, ÀüÀÌÁß Åë½ÅÀ» Áö¿øÇÑ´Ù. Àü¼ÛºÎ´Â »ç¿ëÀÚ ÀÎÅÍÆäÀ̽º·ÎºÎÅÍ 64ºñÆ®ÀÇ µ¥ÀÌÅÍ¿Í 14ºñÆ®ÀÇ Çì´õ Á¤º¸¸¦ ºñµ¿±â FIFO¿¡ ¾²°í, PL4 ÀÎÅÍÆäÀ̽º¸¦ ÅëÇØ DDR µ¥ÀÌÅ͸¦ Àü¼ÛÇÑ´Ù. ±×¸®°í ¼ö½ÅºÎÀÇ µ¿ÀÛÀº Àü¼ÛºÎ¿Í ¿ªÀ¸·Î µ¿ÀÛÇÑ´Ù. Àü¼ÛºÎ¿Í ¼ö½ÅºÎ´Â Ķ·±´õ ¸Þ¸ð¸®¸¦ ÄÁÇDZԷ¹À̼ÇÇÔÀ¸·Î¼ ÃÖ´ë 256°³ÀÇ Ã¤³Î Áö¿øÀÌ °¡´ÉÇÏ°í, ´ë¿ªÆø ÇÒ´çÀ» Á¦¾îÇÒ ¼ö ÀÖµµ·Ï ¼³°èÇÏ¿´´Ù DIP-4 ¹× DIP-2 Æи®Æ¼ »ý¼º ¹× üũ¸¦ ÀÚµ¿ÀûÀ¸·Î ¼öÇàÇϵµ·Ï ±¸ÇöÇÏ¿´´Ù. ¼³°èµÈ ÄÚ¾î´Â ÀÚÀϸµ½º ISE 5.li ÅøÀ» ÀÌ¿ëÇÏ¿© VHDL¾ð¾î¸¦ »ç¿ëÇÏ¿© ±â¼úÇÏ¿´À¸¸ç, Model_SIM 5.6a¸¦ ÀÌ¿ëÇÏ¿© ½Ã¹Ä·¹ÀÌ¼Ç ÇÏ¿´´Ù. ¼³°èµÈ ÄÚ¾î´Â ¶óÀδç 720MbpsÀÇ µ¥ÀÌÅÍ À²·Î µ¿ÀÛÇÏ¿´´Ù. µû¶ó¼ ÃÑ 11.52GbpsÀÇ ´ë¿ªÆøÀ» Áö¿øÇÒ ¼ö ÀÖ´Ù. SPI-4.2 ÀÎÅÍÆäÀ̽º ÄÚ¾î´Â ±â°¡ºñÆ®/Å׶óºñÆ® ¶ó¿ìÅÍ, ±¤ÇÐ Å©·Î½º¹Ù ½ºÀ§Ä¡ ¹× SONET/SDH ±â¹ÝÀÇ Àü¼Û ½Ã½ºÅÛ¿¡¼ ¶óÀÎÄ«µå·Î »ç¿ëÇÒ °æ¿ì ÀûÇÕÇÒ °ÍÀ¸·Î »ç·áµÈ´Ù. |
¿µ¹®³»¿ë (English Abstract) |
System Packet Interface Level 4 Phase 2(SPI-4.2) is an interface for packet and cell transfer between a physical layer(PHY) device and a link layer device, for aggregate bandwidths of OC-192 ATM and Packet Over Sonet/SDH(POS), as well as 10Gbps Ethernet applications. SPI-4.2 core consists of Tx and Rx modules and supports full duplex communication. Tx module of SPI-4.2 core writes 64-bit data word and 14-bit header information from the user interface into asynchronous FIFO and transmits DDR(Double Data Rate) data over PL4 interface. Rx module of SPI-4.2 core operates in vice versa. Tx and Rx modules of SPI-4.2 core are designed to support maximum 256-channel and control the bandwidth allocation by configuring the calendar memory. Automatic DIP4 and DIP-2 parity generation and checking are implemented within the designed core. The designed core uses Xilinx ISE 5.li tool and is described in VHDL Language and is simulated by Model_SIM 5.6a. The designed core operates at 720Mbps data rate per line, which provides an aggregate bandwidth of 11.52Gbps. SPI-4.2 interface core is suited for line cards in gigabit/terabit routers, and optical cross-connect switches, and SONET/SDH-based transmission systems. |
Å°¿öµå(Keyword) |
SPI-4.2
OC-192 ATM
10Gbps Ethernet
Interface Protocol
Hardware
VHDL
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ÆÄÀÏ÷ºÎ |
PDF ´Ù¿î·Îµå
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