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Ȩ Ȩ > ¿¬±¸¹®Çå > ±¹³» ³í¹®Áö > Çѱ¹Á¤º¸Åë½ÅÇÐȸ ³í¹®Áö (Journal of the Korea Institute of Information and Communication Engineering)

Çѱ¹Á¤º¸Åë½ÅÇÐȸ ³í¹®Áö (Journal of the Korea Institute of Information and Communication Engineering)

Current Result Document : 54 / 128 ÀÌÀü°Ç ÀÌÀü°Ç   ´ÙÀ½°Ç ´ÙÀ½°Ç

ÇѱÛÁ¦¸ñ(Korean Title) AES-128/192/256 Rijndael ºí·Ï¾ÏÈ£ ¾Ë°í¸®µë¿ë ¾ÏÈ£ ÇÁ·Î¼¼¼­
¿µ¹®Á¦¸ñ(English Title) A Cryptoprocessor for AES-128/192/256 Rijndael Block Cipher Algorithm
ÀúÀÚ(Author) ¾ÈÇϱ⠠ ¹Ú±¤È£   ½Å°æ¿í   Ha-Kee Ahn   Kwang-Ho Park   Kyung-Wook Shin  
¿ø¹®¼ö·Ïó(Citation) VOL 06 NO. 03 PP. 0427 ~ 0433 (2002. 05)
Çѱ۳»¿ë
(Korean Abstract)
Â÷¼¼´ë ºí·Ï ¾ÏÈ£ Ç¥ÁØÀÎ AES(Advanced Encryption Standard) Rijndael(¶óÀδÞ) ¾ÏÈ£ ÇÁ·Î¼¼¼­¸¦ ¼³°èÇÏ¿´´Ù. ´ÜÀÏ ¶ó¿îµå ºí·ÏÀ» »ç¿ëÇÏ¿© ¶ó¿îµå º¯È¯À» ¹Ýº¹ ó¸®ÇÏ´Â ±¸Á¶¸¦ üÅÃÇÏ¿© Çϵå¿þ¾î º¹Àâµµ¸¦ ÃÖ¼ÒÈ­ÇÏ¿´´Ù. ¶ÇÇÑ, ¶ó¿îµå º¯È¯ºí·Ï ³»ºÎ¿¡ ¼­ºê ÆÄÀÌÇÁ¶óÀÎ ´Ü°è¸¦ »ðÀÔÇÏ¿© ÇöÀç ¶ó¿îµåÀÇ ÈĹݺΠ¿¬»ê°ú ´ÙÀ½ ¶ó¿îµåÀÇ Àü¹ÝºÎ ¿¬»êÀÌ µ¿½Ã¿¡ 󸮵ǵµ·Ï ÇÏ¿´À¸¸ç, À̸¦ ÅëÇÏ¿© ¾Ï.º¹È£ ó¸®À²ÀÌ Çâ»óµÇµµ·Ï ¼³°èÇÔÀ¸·Î½á, ¸éÀû°ú Àü·Â¼Ò¸ð°¡ ÃÖ¼ÒÈ­µÇµµ·Ï ÇÏ¿´´Ù. 128-b/192-b/256-bÀÇ ¸¶½ºÅÍ Å° ±æÀÌ¿¡ ´ëÇØ ¶ó¿îµå º¯È¯ÀÇ Àü¹ÝºÎ 4Ŭ·Ï Áֱ⿡ on-the-fly ¹æ½ÄÀ¸·Î ¶ó¿îµå Å°¸¦ »ý¼ºÇÒ ¼ö ÀÖ´Â È¿À²ÀûÀÎ Å° ½ºÄÉÁÙ¸µ ȸ·Î¸¦ °í¾ÈÇÏ¿´´Ù. Verilog HDL·Î ¸ðµ¨¸µµÈ ¾ÏÈ£ ÇÁ·Î¼¼¼­´Â FPGA·Î ±¸ÇöÇÏ¿© Á¤»ó µ¿ÀÛÇÔÀ» È®ÀÎÇÏ¿´´Ù. 0.35-§­ CMOS ¼¿ ¶óÀ̺귯¸®·Î ÇÕ¼ºÇÑ °á°ú ¾à 25.000°³ÀÇ °ÔÀÌÆ®·Î ±¸ÇöµÇ¾úÀ¸¸ç, 2.5-V Àü¿øÀü¾Ð¿¡¼­ 220-MHz Ŭ·ÏÀ¸·Î µ¿ÀÛÇÏ¿© ¾à 520-Mbits/secÀÇ ¼º´ÉÀ» °®´Ù.
¿µ¹®³»¿ë
(English Abstract)
This paper describes a design of cryptographic processor that implements the AES(Advanced Encryption Standard) block cipher algorithm "Rijndael". To achieve high throughput rate, a sub-pipeline stage is inserted into the round transformation block, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. For area-efficient and low-power implementation, the round block is designed to share the hardware resources in encryption and decryption. An efficient scheme for on-the-fly key scheduling, which supports the three master-key lengths of 128-b/192-b/256-b, is devised to generate round keys in the first sub-pipeline stage of each round processing. The cryptoprocessor designed in Verilog-HDL was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-§­ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.
Å°¿öµå(Keyword) AES(Advanced Encryption Standard) Block Cipher   Cryptographic Processor   Rijndael Algorithm  
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