Çѱ¹Á¤º¸Åë½ÅÇÐȸ ³í¹®Áö (Journal of the Korea Institute of Information and Communication Engineering)
ÇѱÛÁ¦¸ñ(Korean Title) |
WiMAX/WLAN¿ë ´ÙÁßÇ¥ÁØ LDPC º¹È£±â ¼³°è |
¿µ¹®Á¦¸ñ(English Title) |
A Design of Multi-Standard LDPC Decoder for WiMAX/WLAN |
ÀúÀÚ(Author) |
¼ÁøÈ£
¹ÚÇØ¿ø
½Å°æ¿í
Jin-Ho Seo
Hae-Won Park
Kyung-Wook Shin
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¿ø¹®¼ö·Ïó(Citation) |
VOL 17 NO. 02 PP. 0363 ~ 0371 (2013. 02) |
Çѱ۳»¿ë (Korean Abstract) |
º» ³í¹®¿¡¼´Â IEEE 802.16e ¸ð¹ÙÀÏ WiMAX Ç¥ÁØÀÇ 19°¡Áö ºí·Ï±æÀÌ(576¡2304)¿¡ µû¸¥ 6°¡Áö ºÎÈ£À²(1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6)°ú IEEE 802.11n WLAN Ç¥ÁØÀÇ 3°¡Áö ºí·Ï±æÀÌ(648, 1296, 1944)¿¡ µû¸¥ 4°¡Áö ºÎÈ£À²(1/2, 2/3, 3/4, 5/6)À» Áö¿øÇÏ´Â ´ÙÁßÇ¥ÁØ LDPC º¹È£±â¸¦ ¼³°èÇÏ¿´´Ù. Layered º¹È£¹æ½ÄÀÇ ºí·Ï-½Ã¸®¾ó(ºÎºÐº´·Ä) ±¸Á¶¿Í SM(sign-magnitude) ¼öü°è ±â¹ÝÀÇ DFU(decoding function unit)¸¦ Àû¿ëÇÏ¿© Çϵå¿þ¾î º¹Àâµµ¸¦ ÃÖ¼ÒȽÃÄ×´Ù. ¼³°èµÈ ȸ·Î´Â FPGA ±¸ÇöÀ» ÅëÇØ Çϵå¿þ¾î µ¿ÀÛÀ» °ËÁõÇÏ¿´À¸¸ç, 0.13-§ CMOS ¼¿ ¶óÀ̺귯¸®·Î ÇÕ¼ºÇÑ °á°ú ¾à 312,000 °ÔÀÌÆ®¿Í 70,000 ºñÆ®ÀÇ ¸Þ¸ð¸®·Î ±¸ÇöµÇ¾ú°í, 100 MHz@1.8V·Î µ¿ÀÛÇÏ¿© 79¡210 MbpsÀÇ ¼º´ÉÀ» °®´Â °ÍÀ¸·Î Æò°¡µÇ¾ú´Ù.
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¿µ¹®³»¿ë (English Abstract) |
This paper describes a multi-standard LDPC decoder which supports 19 block lengths(576¡2304) and 6 code rates(1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6) of IEEE 802.16e mobile WiMAX standard and 3 block lengths(648, 1296, 1944) and 4 code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A DFU(decoding function unit) based on sign-magnitude arithmetic is used for hardware reduction. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a 0.13-§ CMOS cell library. It has 312,000 gates and 70,000 bits RAM. The estimated throughput is about 79¡210 Mbps at 100 MHz@1.8v.
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Å°¿öµå(Keyword) |
LDPC
¿¡·¯Á¤Á¤ºÎÈ£
WiMAX
WLAN
ÃÖ¼ÒÇÕ ¾Ë°í¸®µë
layered decoding
LDPC
error correction code
WiMAX
WLAN
min-sum algorithm
layered decoding
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