TIIS (한국인터넷정보학회)
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| 한글제목(Korean Title) |
A Real-Time Histogram Equalization System with Automatic Gain Control Using FPGA |
| 영문제목(English Title) |
A Real-Time Histogram Equalization System with Automatic Gain Control Using FPGA |
| 저자(Author) |
Junguk Cho
Seunghun Jin
Key Ho Kwon and Jae Wook
|
| 원문수록처(Citation) |
VOL 04 NO. 04 PP. 0633 ~ 0654 (2010. 08) |
한글내용
(Korean Abstract) |
|
영문내용
(English Abstract) |
High quality camera images, with good contrast and intensity, are needed to obtain the desired information. Images need to be enhanced when they are dark or bright. The histogram equalization technique, which flattens the density distribution of an image, has been widely used to enhance image contrast due to its effectiveness and simplicity. This technique, however, cannot be used to enhance images that are either too dark or too bright. In addition, it is difficult to perform histogram equalization in real-time using a general-purpose computer. This paper proposes a histogram equalization technique with AGC (Automatic Gain Control) to extend the image enhancement range. It is designed using VHDL (VHSIC Hardware Description Language) to enhance images in real-time. The system is implemented with an FPGA (Field Programmable Gate Array). An image processing system with this FPGA is implemented. The performance of this image processing system is measured. |
| 키워드(Keyword) |
Automatic gain control
image enhancement
FPGA
histogram equalization
VHDL
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| 파일첨부 |
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