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Ȩ Ȩ > ¿¬±¸¹®Çå > ±¹³» ³í¹®Áö > Çѱ¹Á¤º¸Ã³¸®ÇÐȸ ³í¹®Áö > Á¤º¸Ã³¸®ÇÐȸ ³í¹®Áö A

Á¤º¸Ã³¸®ÇÐȸ ³í¹®Áö A

Current Result Document :

ÇѱÛÁ¦¸ñ(Korean Title) µ¿Àû »ç»ó Å×ÀÌºí ±â¹ÝÀÇ ¹öÆÛ±¸Á¶¸¦ ÅëÇÑ Solid State DiskÀÇ ¾²±â ¼º´É Çâ»ó
¿µ¹®Á¦¸ñ(English Title) A Buffer Architecture based on Dynamic Mapping table for Write Performance of Solid State Disk
ÀúÀÚ(Author) Á¶ÀÎÇ¥   °í¼ÒÇâ   ¾çÈƸ𠠠¹Ú±âÈ£   ±è½Å´ö   In-Pyo Cho   So-Hyang Ko   Hoon-Mo Yang   Gi-Ho Park   Shin-Dug Kim  
¿ø¹®¼ö·Ïó(Citation) VOL 18-A NO. 04 PP. 0135 ~ 0142 (2011. 08)
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(Korean Abstract)
º» ¿¬±¸´Â Ç÷¡½Ã ¸Þ¸ð¸® ±â¹ÝÀÇ °í¼º´É SSD (Solid State Disk) ±¸Á¶¸¦ À§ÇÏ¿© µð½ºÅ© ÂüÁ¶ Ư¼º¿¡ ÀûÀÀÀûÀ¸·Î ±¸µ¿ÇÏ´Â È¿À²ÀûÀÎ ¹öÆÛ±¸Á¶¿Í ±¸µ¿ ±â¹ýÀ» ¼³°èÇÑ´Ù. ±âÁ¸ SSD´Â »èÁ¦µ¿ÀÛ È½¼öÀÇ Á¦¾àÀº ¹°·Ð Àбâ¿Í ¾²±â µ¿ÀÛ¿¡ ´ëÇÏ¿© ºñ´ëĪÀûÀÎ ¼º´ÉÀ» º¸À̴ Ư¡À» °®°í ÀÖ´Ù. ÀÌ·¯ÇÑ »èÁ¦µ¿ÀÛ È½¼ö¿Í ¾²±â µ¿ÀÛÀÇ Áö¿¬½Ã°£À» ÃÖ¼ÒÈ­ Çϱâ À§Çؼ­´Â ´ÙÁß Ç÷¡½Ã ¸Þ¸ð¸® Ĩµé¿¡ ´ëÇØ ¾²±â µ¿ÀÛÀº º´·ÄÀûÀ¸·Î ¼öÇàÇÏ´Â Á¤µµ¸¦ ÃÖ´ëÈ­ÇÏ¿© ¿î¿µÇÏ¿©¾ß ÇÑ´Ù. µû¶ó¼­ Ç÷¡½Ã ¸Þ¸ð¸® Ĩµé¿¡ ´ëÇÑ ÀÎÅ͸®ºù ·¹º§ (interleaving level)À» ÃÖ´ëÈ­ Çϱâ À§ÇÏ¿©, º» ³í¹®¿¡¼­´Â È¥ÇÕ À§Ä¡ »ç»ó ±â¹ý (hybrid address mapping)°ú ½´ÆÛ ºí·Ï (super-block) ±â¹ÝÀÇ SSD ±¸Á¶¿¡ ´ëÇÏ¿© ¼º´É Áõ´ë¿Í Áõ°¡µÈ ÀåÄ¡ ¼ö¸íÀ» Á¦°øÇϱâ À§ÇÑ È¿À²Àû ¹öÆÛ ±¸Á¶¸¦ Á¦¾ÈÇÑ´Ù. Á¦¾ÈÇÑ ¹öÆÛ±¸Á¶´Â ÀÀ¿ë ¼öÇàƯ¼ºÀ» ±â¹ÝÀ¸·Î ÃÖÀûÀÇ ÀÓÀÇ/¼øÂ÷¾²±â¸¦ ±¸ºÐÇϸç, ¼öÇà ¼º´É¿¡ Áß¿äÇÑ ¼øÂ÷¾²±â Á¤µµÀÇ Å©±â¸¦ Áõ´ë½ÃÅ°´Â µ¿Àû À¶ÇÕ ¹æ¹ý, ±¸µ¿µÇ´Â ¹öÆÛ±¸Á¶¿Í »ç»ó Å×À̺íÀÇ È¿À²ÀûÀÎ °ü¸® ±¸Á¶¸¦ ¼³°èÇÏ¿´À¸¸ç, À̸¦ ÅëÇØ ±âÁ¸ÀÇ ´Ü¼øÇÑ ¹öÆÛ ¿î¿µ±â¹ý¿¡ ºñÇÏ¿© 35%ÀÇ ¼º´ÉÇâ»óÀ» Á¦°øÇÑ´Ù.
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(English Abstract)
This research is to design an effective buffer structure and its management for flash memory based high performance SSDs (Solid State Disks). Specifically conventional SSDs tend to show asymmetrical performance in read and /write operations, in addition to a limited number of erase operations. To minimize the number of erase operations and write latency, the degree of interleaving levels over multiple flash memory chips should be maximized. Thus, to increase the interleaving effect, an effective buffer structure is proposed for the SSD with a hybrid address mapping scheme and super-block management. The proposed buffer operation is designed to provide performance improvement and enhanced flash memory life cycle. Also its management is based on a new selection scheme to determine random and sequential accesses, depending on execution characteristics, and a method to enhance the size of sequential access unit by aggressive merging. Experiments show that a newly developed mapping table under the MBA is more efficient than the basic simple management in terms of maintenance and performance. The overall performance is increased by around 35% in comparison with the basic simple management.
Å°¿öµå(Keyword) ´ë¿ë·® ÀúÀåÀåÄ¡   ºñ Èֹ߼º ¸Þ¸ð¸®   ¹öÆÛ °ü¸® ±¸Á¶   ÀÎÅ͸®ºù   ¼º´É ºÐ¼®   Solid State Disks   Non-Volatile Memory   Buffer Management   Interleaving   Performance Evaluation  
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