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Ȩ Ȩ > ¿¬±¸¹®Çå > ±¹³» ³í¹®Áö > Çѱ¹Á¤º¸°úÇÐȸ ³í¹®Áö > Á¤º¸°úÇÐȸ ³í¹®Áö C : ÄÄÇ»ÆÃÀÇ ½ÇÁ¦

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Current Result Document : 5 / 7 ÀÌÀü°Ç ÀÌÀü°Ç   ´ÙÀ½°Ç ´ÙÀ½°Ç

ÇѱÛÁ¦¸ñ(Korean Title) Ç÷¡½Ã ¸Þ¸ð¸®¸¦ À§ÇÑ È¿À²ÀûÀÎ ¼±¹ÝÀÔ°ú ºñµ¿±â ¾²±â ±â¹ý
¿µ¹®Á¦¸ñ(English Title) Efficient Prefetching and Asynchronous Writing for Flash Memory
ÀúÀÚ(Author) ¹Ú±¤Èñ   ±è´öȯ   Kwanghee Park   Deokhwan Kim  
¿ø¹®¼ö·Ïó(Citation) VOL 15 NO. 02 PP. 0077 ~ 0088 (2009. 02)
Çѱ۳»¿ë
(Korean Abstract)
ÈÞ´ë¿ë ÀúÀåÀåÄ¡·Î °¢±¤ ¹Þ°í ÀÖ´Â NAND Ç÷¡½Ã ¸Þ¸ð¸®ÀÇ ¿ë·®ÀÌ Ä¿Áö¸é¼­ ±âÁ¸ÀÇ ÆÄÀϽýºÅÛ°ú Ç÷¡½Ã ¸Þ¸ð¸® ÄÁÆ®·Ñ·¯ °£ÀÇ Áß°£ ¸Å°³Ã¼ ¿ªÇÒÀ» ÇØÁÖ´Â FTL(Flash Translation Layer)ÀÇ ÁÖ¼Ò º¯È¯ ¹× ¼ö¸í °ü¸® ±â¹ýÀÌ Á¡Â÷ Áß¿äÇØÁö°í ÀÖ´Ù. º» ³í¹®¿¡¼­´Â ¿¬¼ÓÀûÀÎ ³í¸® ÁÖ¼Ò ¿äûÀÌ ¹°¸® ÁÖ¼Ò°¡ ÀÎÁ¢ÇÑ °æ¿ìÀÇ °ªÀ» ±â·ÏÇÏ´Â ¿¬¼Ó¼º Ä«¿îÅ͸¦ Á¦¾ÈÇÏ¿© ÁÖ¼Ò º¯È¯ Ƚ¼ö¸¦ °¨¼Ò ½ÃÄ×À¸¸ç ÀÌ¿Í ÇÔ²² ÀÚÁÖ ¾²ÀÌ´Â ÁÖ¼ÒÀÇ ÆäÀÌÁöµéÀ» ¹Ì¸® ÁÖ ¸Þ¸ð¸®¿¡ ¼±¹ÝÀÔÇÏ¿© Ç÷¡½Ã ¸Þ¸ð¸®ÀÇ ÀÔÃâ·Â ¼º´ÉÀ» Çâ»ó½ÃÄ×´Ù. ¶ÇÇÑ ¾²±â ºóµµ°¡ ³ôÀº ÁÖ¼Ò¸¦ ¿¹ÃøÇÏ°í ÀæÀº ¾²±â¸¦ ¹æÁöÇϱâ À§ÇØ 2ºñÆ® ¾²±â ¿¹Ãø°ú ºñµ¿±â ¾²±â ±â¹ýÀ» Á¦½ÃÇÏ¿© ¾²±â ¼º´É°ú Ç÷¡½Ã ¸Þ¸ð¸®ÀÇ ¼ö¸íÀ» Çâ»ó ½ÃÄ×´Ù. ½ÇÇè °á°ú º» ³í¹®¿¡¼­ Á¦¾ÈÇÏ´Â CFTL (Clustered Flash Translation Layer)ÀÌ ±âÁ¸ FTLµéº¸´Ù ÁÖ¼Ò º¯È¯ ¼º´ÉÀÌ ÃÖ´ë 20%, ¾²±â ½Ã°£À» ÃÖ´ë 50% ÀÌ»ó °¨¼Ò½ÃÄ×´Ù.
¿µ¹®³»¿ë
(English Abstract)
According to the size of NAND flash memory as the storage system of mobile device becomes large, the performance of address translation and life cycle management in FTL (Flash Translation Layer) to interact with file system becomes very important. In this paper, we propose the continuity counters, which represent the number of continuous physical blocks whose logical addresses are consecutive, to reduce the number of address translation. Furthermore we propose the prefetching method which preloads frequently accessed pages into main memory to enhance I/O performance of flash memory. Besides, we use the 2-bit write prediction and asynchronous writing method to predict addresses repeatedly referenced from host and prevent from writing overhead. The experiments show that the proposed method improves the I/O performance and extends the life cycle of flash memory. As a result, proposed CFTL (Clustered Flash Translation Layer)¡¯s performance of address translation is faster 20% than conventional FTLs. Furthermore, CFTL is reduced about 50% writing time than that of conventional FTLs.
Å°¿öµå(Keyword) Ç÷¡½Ã º¯È¯ °èÃþ   FTL   ±ºÁýÇü Çؽà Å×ÀÌºí   Clustered hash table   ¼±¹ÝÀÔ   Prefetch   2ºñÆ® ¾²±â ¿¹Ãø   2-bit write prediction  
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