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ÇѱÛÁ¦¸ñ(Korean Title) |
¸ð¹ÙÀÏ ³»ÀåÇü ½Ã½ºÅÛÀ» À§ÇÑ µà¾ó-Æ÷Æ®SDRAMÀÇ ¼º´É Æò°¡ ¹× ÃÖÀûÈ |
¿µ¹®Á¦¸ñ(English Title) |
Performance Evaluation and Optimization of Dual-Port SDRAM Architecture for Mobile Embedded Systems |
ÀúÀÚ(Author) |
¾çȸ¼®
±è¼ºÂù
¹ÚÇØ¿ì
±èÁø¿ì
Çϼøȸ
Hoeseok Yang
Sungchan Kim
Haewoo Park
Soonhoi Ha
Jinwoo Kim
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¿ø¹®¼ö·Ïó(Citation) |
VOL 14 NO. 05 PP. 0542 ~ 0546 (2008. 07) |
Çѱ۳»¿ë (Korean Abstract) |
ÃÖ±Ù µà¾ó-ÇÁ·Î¼¼¼ ±â¹ÝÀÇ ¸ð¹ÙÀÏ ³»ÀåÇü ½Ã½ºÅÛÀ» À§ÇÑ µà¾ó-Æ÷Æ®SDRAMÀÌ ¹ßÇ¥ µÇ¾ú´Ù. ÀÌ´Â ´ÜÀÏ ¸Þ¸ð¸® ĨÀÌ µÎ ÇÁ·Î¼¼¼ÀÇ ·ÎÄà ¸Þ¸ð¸®¿Í °øÀ¯ ¸Þ¸ð¸® ¿ªÇÒÀ» ¸ðµÎ ´ã´çÇϹǷΠ°øÀ¯ ¸Þ¸ð¸®¸¦ À§ÇÏ¿© Ãß°¡ÀÇ SRAM ¸Þ¸ð¸®¸¦ »ç¿ëÇÏ´Â ±âÁ¸ÀÇ ±¸Á¶¿¡ ºñÇØ ´õ °£´ÜÇÑ Åë½Å ±¸Á¶ÀÌ´Ù. ¾ç Æ÷Æ®·ÎºÎÅÍÀÇ µ¿½ÃÀûÀÎ Á¢±Ù¿¡¼ÀÇ »óÈ£ ¹èŸ¼ºÀ» º¸ÀåÇϱâ À§ÇÏ¿© ¸ðµç °øÀ¯ ¸Þ¸ð¸® Á¢±Ù¿¡´Â Ư¼öÇÑ µ¿±âÈ ±â¹ýÀÌ ¼ö¹ÝµÇ¾î¾ß Çϴµ¥ ÀÌ´Â ÀáÀçÀûÀÎ ¼º´É ¾ÇÈÀÇ ¿øÀÎÀÌ µÈ´Ù. ÀÌ ³í¹®¿¡¼´Â ÀÌ·¯ÇÑ µ¿±âÈ ºñ¿ëÀ» °í·ÁÇÏ¿© µà¾ó-Æ÷Æ®SDRAM ±¸Á¶ÀÇ ¼º´ÉÀ» Æò°¡ÇÏ°í, ÁÖ ÀÀ¿ëÀÇ Åë½Å Ư¼ºÀ» °í·ÁÇÏ¿© ÃÖÀûÈÇÑ ¶ô¿ì¼±±Ç ±â¹ý°ú Á¤Àûº¹»ç ±â¹ýÀ» Á¦¾ÈÇÑ´Ù. ´õ ³ª¾Æ°¡, °øÀ¯ ¹ðÅ©¸¦ ¿©·¯ ºí·ÏÀ¸·Î ³ª´®À¸·Î½á ¼·Î ´Ù¸¥ ºí·Ïµé¿¡ ´ëÇÑ µ¿½ÃÀûÀÎ Á¢±ÙÀ» °¡´ÉÄÉ ÇÏ¿© ¼º´ÉÀ» °³¼±Çϵµ·Ï ÇÑ´Ù. °¡»ó ÇÁ·ÎÅäŸÀÌÇΠȯ°æ¿¡¼ ¼öÇàµÈ ½ÇÇèÀº ÀÌ·¯ÇÑ ÃÖÀûÈ ±â¹ýµéÀÌ ±âº» µà¾ó-Æ÷Æ®SDRAM ±¸Á¶¿¡ ºñÇÏ¿© 20-50%ÀÇ ¼º´É Çâ»óÀ» °¡Á®¿ÈÀ» º¸¿©ÁØ´Ù. |
¿µ¹®³»¿ë (English Abstract) |
Recently dual-port SDRAM (DPSDRAM) architecture tailored for dual-processor based mobile embedded systems has been announced where a single memory chip plays the role of the local memories and the shared memory for both processors. In order to maintain memory consistency from simultaneous accesses of both ports, every access to the shared memory should be protected by a synchronization mechanism, which can result in substantial access latency. We propose two optimization techniques by exploiting the communication patterns of target applications: lock-priority scheme and static-copy scheme. Further, by dividing the shared bank into multiple blocks, we allow simultaneous accesses to different blocks thus achieve considerable performance gain. Experiments on a virtual prototyping system show a promising result - we could achieve about 20-50% performance gain compared to the base DPSDRAM architecture. |
Å°¿öµå(Keyword) |
¸Þ¸ð¸® ±¸Á¶
µà¾ó-Æ÷Æ®SDRAM
¸ð¹ÙÀÏ ³»ÀåÇü ½Ã½ºÅÛ
Memory Architecture
Dual-port SDRAM
Mobile Embedded System
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ÆÄÀÏ÷ºÎ |
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