Á¤º¸°úÇÐȸ ³í¹®Áö C : ÄÄÇ»ÆÃÀÇ ½ÇÁ¦
Current Result Document : 3 / 4
ÇѱÛÁ¦¸ñ(Korean Title) |
128-ºñÆ® ºí·Ï ¾ÏÈ£È ¾Ë°í¸®Áò SEEDÀÇ Àú¸éÀû °í¼º´É Çϵå¿þ¾î ±¸Á¶¸¦ À§ÇÑ Çϵå¿þ¾î ¼³°è °ø°£ Ž»ö |
¿µ¹®Á¦¸ñ(English Title) |
A Hardware Design Space Exploration toward Low-Area and High-Performance Architecture for the 128-bit Block Cipher Algorithm SEED |
ÀúÀÚ(Author) |
ÀÌ°
|
¿ø¹®¼ö·Ïó(Citation) |
VOL 13 NO. 04 PP. 0231 ~ 0239 (2007. 08) |
Çѱ۳»¿ë (Korean Abstract) |
º» ³í¹®¿¡¼´Â ±¹³» Ç¥ÁØ 128ºñÆ® ºí·Ï ¾ÏÈ£È ¾Ë°í¸®ÁòÀÎ SEED¸¦ Çϵå¿þ¾î·Î ¼³°èÇÒ °æ¿ì ¸éÀû-¼º´É °£ÀÇ trade-off °ü°è¸¦ º¸¿©ÁØ´Ù. º» ³í¹®¿¡¼ ´ÙÀ½ 4°¡Áö À¯ÇüÀÇ ¼³°è ±¸Á¶¸¦ ºñ±³ÇÑ´Ù. (1) Design 1 : 16 ¶ó¿îµå ¿ÏÀü ÆÄÀÌÇÁ¶óÀÎ ¹æ½Ä, (2) Design 2 : ´ÜÀÏ ¶ó¿îµåÀÇ ¹Ýº¹ »ç¿ë ¹æ½Ä (3) Design 3 : G ÇÔ¼ö °øÀ¯ ¹× ¹Ýº¹ »ç¿ë ¹æ½Ä (4) Design 4 : ´ÜÀÏ ¶ó¿îµå ³»ºÎ ÆÄÀÌÇÁ¶óÀÎ ¹æ½Ä. (1),(2),(3)ÀÇ ¹æ½ÄÀº ±âÁ¸ÀÇ ³í¹®µé¿¡¼ Á¦¾ÈÇÑ °¢±â ´Ù¸¥ ¼³°è ¹æ½ÄÀ̸ç (4)¹ø ¼³°è ¹æ½ÄÀÌ º» ³í¹®¿¡¼ »õ·Ó°Ô Á¦¾ÈÇÑ ¼³°è ¹æ½ÄÀÌ´Ù. º» ³í¹®¿¡¼ »õ·Ó°Ô Á¦¾ÈÇÑ ¹æ½ÄÀº, F ÇÔ¼ö ³»ÀÇ G ÇÔ¼öµéÀ» ÆÄÀÌÇÁ¶óÀÎ ¹æ½ÄÀ¸·Î ¿¬°áÇÏ¿© ¸éÀû ¿ä±¸·®À» (2)¹ø¿¡ ºñÇؼ ´ÃÀÌÁö ¾ÊÀ¸¸é¼µµ ÆÄÀÌÇÁ¶óÀΰú °øÀ¯ºí·Ï »ç¿ëÀÇ È¿°ú·Î ¼º´ÉÀ» Design 2¿Í Design 3º¸´Ù ³ôÀÎ ¼³°è ¹æ½ÄÀÌ´Ù. º» ³í¹®¿¡¼ 4°¡Áö °¢±â ´Ù¸¥ ¹æ½ÄÀ» °¢°¢ ½ÇÁ¦ Çϵå¿þ¾î·Î ¼³°èÇÏ°í FPGA·Î ±¸ÇöÇÏ¿© ¼º´É ¹× ¸éÀû ¿ä±¸·®À» ºñ±³ ºÐ¼®ÇÑ´Ù. ½ÇÇè ºÐ¼® °á°ú, º» ³í¹®¿¡¼ »õ·Î Á¦¾ÈÇÑ F ÇÔ¼ö ³»ºÎ 3´Ü ÆÄÀÌÇÁ¶óÀÎ ¹æ½ÄÀÌ Design 1 ¹æ½ÄÀ» Á¦¿ÜÇÏ°í °¡Àå throughput ÀÌ ³ô´Ù. Á¦¾ÈµÈ Design 4 °¡ ´ÜÀ§ ¸éÀû´ç Ãâ·Â¼º´É(throughput)¸é¿¡¼ ´Ù¸¥ ¸ðµç ¼³°è ¹æ½Ä¿¡ ºñÇؼ ÃÖ´ë 2.8¹è ¿ì¼öÇÏ´Ù. µû¶ó¼, »õ·ÎÀÌ Á¦¾ÈµÈ SEED ¼³°è°¡ ±âÁ¸ÀÇ ¼³°è ¹æ½Äµé¿¡ ºñÇؼ ¸éÀû´ëºñ ¼º´ÉÀÌ °¡Àå È¿À²ÀûÀ̶ó°í ÇÒ ¼ö ÀÖ´Ù. |
¿µ¹®³»¿ë (English Abstract) |
This paper presents the trade-off relationship between area and performance in the hardware design space exploration for the Korean national standard 128-bit block cipher algorithm SEED. In this paper, we compare the following four hardware design types of SEED algorithm : (1) Design 1 that is 16 round fully pipelining approach, (2) Design 2 that is a one round looping approach, (3) Design 3 that is a G function sharing and looping approach, and (4) Design 4 that is one round with internal 3 stage pipelining approach. The Design 1, Design 2, and Design 3 are the existing design approaches while the Design 4 is the newly proposed design in this paper. Our new design employs the pipeline between three G-functions and adders consisting of a F function, which results in the less area requirement than Design 2 and achieves the higher performance than Design 2 and Design 3 due to pipelining and module sharing techniques. We design and implement all the comparing four approaches with real hardware targeting FPGA for the purpose of exact performance and area analysis. The experimental results show that Design 4 has the highest performance except Design 1 which pursues very aggressive parallelism at the expanse of area. Our proposed design (Design 4) shows the best throughput/area ratio among all the alternatives by 2.8 times. Therefore, our new design for SEED is the most efficient design comparing with the existing designs. |
Å°¿öµå(Keyword) |
SEED
128 ºñÆ® ´ëĪÇü ºí·Ï ¾ÏÈ£È ¾Ë°í¸®Áò
¸éÀû°ú ¼º´ÉÀÇ trade-offs
Çϵå¿þ¾î ¼³°è °ø°£ Ž»ö
³»ÀåÇü ½Ã½ºÅÛ
¾ÏÈ£È ÇÁ·Î¼¼¼
SEED
128-bit symmetric block cipher algorithm
FPGA
hardware design space exploration
area-performance trade-offs
cryptography processor
|
ÆÄÀÏ÷ºÎ |
PDF ´Ù¿î·Îµå
|