Current Result Document :
| 한글제목(Korean Title) |
KB1 암호알고리즘의 하드웨어 구현 |
| 영문제목(English Title) |
Hardware Design of KB1 Cryptographic Algorithm |
| 저자(Author) |
하창수
최병윤
Chang-Soo Ha
Byeong-Yoon Choi
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| 원문수록처(Citation) |
VOL 17 NO. 01 PP. VE ~ 0002 (2007. 04) |
한글내용
(Korean Abstract) |
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영문내용
(English Abstract) |
In this paper, we design hardware of KB1-final symmetric cryptographic algorithm and analyze performance of the KB1-final that is being developed in Korea for RFID/USN system. KB1-final represent the last KB1 algorithm that improved KB1-80 and KB1-128 algorithm. To analyze pure effectiveness of the hardware design of KB1 cryptographic algorithm, we design and analyze hardware of KB1 that only supports ECB (Electronic Codebook) mode. For hardware design of KB1-final, first we take the KB1-final algorithm apart and generate test vectors using C language, second we describe KB1-final hardware using verilog HDL, then we simulate it and the simulation results compare with test vectors. The KB1-final hardware is synthesized by IDEC Samsung 0.35um CMOS standard cell libraries. KB1-final has 3,823 gates and about 7.96ns critical path delay. It is about 125Mhz. Encryption and decryption performance is about 235 Mbps.
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