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Current Result Document :
ÇѱÛÁ¦¸ñ(Korean Title) |
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¿µ¹®Á¦¸ñ(English Title) |
Fast locking PLL with time difference detector |
ÀúÀÚ(Author) |
°í±â¿µ
ÃÖÇõȯ
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Gi-Yeong Ko
Hyuk-Hwan Choi
Young-Shig Choi
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¿ø¹®¼ö·Ïó(Citation) |
VOL 21 NO. 01 PP. 0691 ~ 0693 (2017. 06) |
Çѱ۳»¿ë (Korean Abstract) |
º» ³í¹®¿¡¼´Â ½Ã°£ Â÷ °¨Áö±â¿Í LSI(Lock Status Indicator)¸¦ »ç¿ëÇÏ¿© ºü¸¥ À§»ó°íÁ¤ ½Ã°£À» °®´Â À§»ó°íÁ¤·çÇÁ¸¦ Á¦¾ÈÇÏ¿´´Ù. Á¦¾ÈµÈ À§»ó°íÁ¤·çÇÁ´Â 1.8V 0.18¥ìm CMOS °øÁ¤À» »ç¿ëÇÏ¿© ¼³°èÇÏ¿´°í, Hspice ½Ã¹Ä·¹À̼ÇÀ» ÅëÇØ È¸·ÎÀÇ µ¿ÀÛÀ» °ËÁõÇÏ¿´´Ù.´ÙÀ½Àº ¿ä¾à¹®ÀÔ´Ï´Ù.
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¿µ¹®³»¿ë (English Abstract) |
A novel structure of fast locking phase locked loop (PLL) with time difference detector and Lock status indicator (LSI) is proposed in this paper. Fast locking time is achieved using LSI. It has been simulated and proved by HSPICE in a CMOS 0.18¥ìm 1.8V process.
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Å°¿öµå(Keyword) |
PLL
fast locking time
small size chip
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PDF ´Ù¿î·Îµå
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