2011³â Ãá°èÇмú´ëȸ
Current Result Document :
ÇѱÛÁ¦¸ñ(Korean Title) |
0.18§ Generic °øÁ¤ ±â¹ÝÀÇ 8ºñÆ® eFuse OTP Memory ¼³°è |
¿µ¹®Á¦¸ñ(English Title) |
Design of an eFuse OTP Memory of 8bits Based on a Generic Process |
ÀúÀÚ(Author) |
ÀåÁöÇý
±è±¤ÀÏ
ÀüȲ°ï
ÇÏÆǺÀ
±è¿µÈñ
Ji-Hye Jang
Kwang-Il Kim
Hwang-Gon Jeon
Pan-Bong Ha
Young-Hee Kim
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¿ø¹®¼ö·Ïó(Citation) |
VOL 15 NO. 01 PP. 0687 ~ 0691 (2011. 05) |
Çѱ۳»¿ë (Korean Abstract) |
º» ³í¹®¿¡¼´Â ¾Æ³¯·Î±× Æ®¸®¹Ö¿ëÀ¸·Î »ç¿ëµÇ´Â 0.18§ generic °øÁ¤ ±â¹ÝÀÇ EM (Electro-Migration)°ú eFuseÀÇ ÀúÇ× º¯µ¿À» °í·ÁÇÑ 8bit eFuse OTP (One-Time Programmable) ¸Þ¸ð¸®¸¦ ¼³°èÇÏ¿´´Ù. eFuse OTP ¸Þ¸ð¸®´Â eFuse¿¡ Àΰ¡µÇ´Â program power¸¦ Áõ°¡½ÃÅ°±â À§ÇØ external program voltage¸¦ »ç¿ëÇÏ¿´À¸¸ç, ÇÁ·Î±×·¥µÇÁö ¾ÊÀº cell¿¡ È帣´Â read current¸¦ ³·Ãß±â À§ÇØ RWL (Read Word-Line) activation ÀÌÀü¿¡ BLÀ» VSS·Î prechargingÇÏ´Â ¹æ½Ä°ú read NMOS transistor¸¦ ÃÖÀûÈ ¼³°èÇÏ¿´´Ù. ±×¸®°í ÇÁ·Î±×·¥µÈ eFuse ÀúÇ×ÀÇ º¯µ¿À» °í·ÁÇÑ variable pull-up load¸¦ °®´Â sensing margin test ȸ·Î¸¦ ¼³°èÇÏ¿´´Ù. ÇÑÆí eFuse linkÀÇ length¸¦ splitÇÏ¿© eFuse OTPÀÇ ÇÁ·Î±×·¥ ¼öÀ² (program yield)À» ³ô¿´´Ù.
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¿µ¹®³»¿ë (English Abstract) |
In this paper, we design an 8-bit eSuse OTP (one-time programmable) memory in consideration of EM (electro-migration) and eFuse resistance variation based on a 0.18§ generic process, which is used for an analog trimming application. First, we use an external program voltage to increase the program power applied an eFuse. Secondly, we apply a scheme of precharging BL to VSS prior to RWL (read word line) activation and optimize read NMOS transistors to reduce the read current flowing through a non-programmed cell. Thirdly, we design a sensing margin test circuit with a variable pull-up load out of consideration for the eFuse resistance variation of a programmed eFuse. Finally, we increase program yield of eFuse OTP memory by splitting the length of an eFuse link.
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Å°¿öµå(Keyword) |
eFuse OTP
generic process
Electro-Migration
Variable pull-up load
Program yield
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ÆÄÀÏ÷ºÎ |
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