Journal of EEIS
Current Result Document : 10 / 10
| 한글제목(Korean Title) |
Fast and Accurate Delay Estimation for Digital CMOS VLSI |
| 영문제목(English Title) |
Fast and Accurate Delay Estimation for Digital CMOS VLSI |
| 저자(Author) |
Dong-Wook Kim
Tae-Yong Choi
Byoung-Kwon Jung
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| 원문수록처(Citation) |
VOL 03 NO. 04 PP. 0433 ~ 0441 (1998. 08) |
한글내용
(Korean Abstract) |
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영문내용
(English Abstract) |
Performance prediction for digital designs has become more complex and cost-consuming as the circuit size increases. This paper is concerned with the circuit delay estimation at the gate level, which is one of the important factors in performance prediction. A delay model for digital CMOS circuits is proposed here, which can predict the delay efficiently and accurately for the wide range of input transition time, transistor size, and output load. This paper, first, constructs a delay model for the CMOS inverter, and then it is extended to other logic gates by converting the gate to an equivalent inverter. The performance of the model was compared with the SPICE simulation results to show how the model competes with SPICE in terms of efficiency and accuracy. Experimental results show that the proposed model has the accuracy of less than 5% relative error and is 70 times faster, compared with SPICE.
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| 키워드(Keyword) |
CAD
Delay Estimation
Digital CMOS VLSI
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| 파일첨부 |
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