Journal of EEIS
Current Result Document :
| 한글제목(Korean Title) |
Dual-Gate Surface Channel 0.1㎛ CMOSFETs |
| 영문제목(English Title) |
Dual-Gate Surface Channel 0.1㎛ CMOSFETs |
| 저자(Author) |
Hyouk Man Kwon
Yeong-Taek Lee
Jong Duk Lee
Byung-Gook Park
|
| 원문수록처(Citation) |
VOL 03 NO. 02 PP. 0261 ~ 0266 (1998. 04) |
한글내용
(Korean Abstract) |
|
영문내용
(English Abstract) |
This paper describes the fabrication and characterization of dual-polysilicon gated surface channel 0.1%u339B CMOSFETs using BF2 and arsenic as channel dopants. We have used an LDD structure and 40 %u212B gate oxide as an insulator. To suppress short channel effects down to 0.1%u339B channel length, shallow source/drain extensions implemented by low energy implantation and SSR(Super Steep Retrograde) channel structure were used. The threshold voltages of fabricated CMOSFETs are 0.6V. The maximum transconductance of nMOSFET is 315%u03BCS/%u339B, and that of pMOSFET is 156 %u03BCS/%u339B. The drain saturation current of 418 %u3382/%u339B, 187 %u3382/%u339B are obtained. Subthreshold swing is 85mV/dec and 88mV/dec, respectively. DIBL(Drain Induced Barrier Lowering) is below 100mV. In the device with 2000%u212B thick gate polysilicon, depletion in polysilicon near the gate oxide results in an increase of equivalent gate oxide thickness and degradation of device characteristics. The gate delay time is measured to be 336psec at operation voltage of 2V.
|
| 키워드(Keyword) |
Semiconductors
Materials
and Components
Dual-Gate Surface Channel
CMOSFETs
|
| 파일첨부 |
PDF 다운로드
|
