| 한글제목(Korean Title) |
Dynamic Voltage and Frequency Scaling for Power-Constrained Design using Process Voltage and Temperature Sensor Circuits |
| 영문제목(English Title) |
Dynamic Voltage and Frequency Scaling for Power-Constrained Design using Process Voltage and Temperature Sensor Circuits |
| 저자(Author) |
Haiqing Nan
Kyung Ki Kim
Wei Wang
Ken Choi
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| 원문수록처(Citation) |
VOL 07 NO. 01 PP. 0093 ~ 0102 (2011. 03) |
한글내용
(Korean Abstract) |
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영문내용
(English Abstract) |
In deeply scaled CMOS technologies, two major non-ideal factors are threatening the survival of the CMOS; i) PVT (process, voltage, and temperature) variations and ii) leakage power consumption. In this paper, we propose a novel postsilicon tuning methodology to scale optimum voltage and frequency “dynamically”. The proposed design technique will use our PVT sensor circuits to monitor the variations and based on the monitored variation data, voltage and frequency will be compensated “automatically”. During the compensation process, supply voltage is dynamically adjusted to guarantee the minimum total power consumption without violating the frequency requirement. The simulation results show that the proposed technique can reduce the total power by 85% and the static power by 53% on average for the selected ISCAS’85 benchmark circuits with 45 nm CMOS technology compared to the results of the traditional PVT compensation method.
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| 키워드(Keyword) |
PVT Variation se nsors
Yield
Voltage Scaling
Frequency Scaling
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| 파일첨부 |
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