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Current Result Document :
ÇѱÛÁ¦¸ñ(Korean Title) |
°í¼Ó RISC ÇÁ·Î¼¼¼¸¦ À§ÇÑ °¡»ó ij½¬ ±¸Á¶ |
¿µ¹®Á¦¸ñ(English Title) |
A Virtual Cache Architecture for Fast RISC Processors |
ÀúÀÚ(Author) |
±èµ¿¿í
ÀÌÁØ¿ø
¹Ú½Â±Ô
Dongwook Kim
Joonwon Lee
Seungkyu Park
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¿ø¹®¼ö·Ïó(Citation) |
VOL 23 NO. 09 PP. 0887 ~ 0898 (1996. 09) |
Çѱ۳»¿ë (Korean Abstract) |
º» ³í¹®¿¡¼´Â ij½¬ ¾×¼¼½º ½Ã°£ÀÌ direct-mapped ij½¬¿Í °°ÀÌ ºü¸£¸é¼, ij½¬ ¼º°øÀ²Àº set-associative ij½¬Ã³·³ ³ôÀº, °í¼Ó RISC ÇÁ·Î¼¼¼¸¦ À§ÇÑ »õ·Î¿î °¡»ó ij½¬ ±¸Á¶¸¦ Á¦¾ÈÇÑ´Ù. ÀÌ ±¸Á¶¿¡¼´Â Àüü ij½¬ ¸Þ¸ð¸®¸¦ n°³ÀÇ ¹ðÅ©·Î ³ª´©°í, °¢ ÇÁ·Î¼¼½º »ý¼º½Ã¿¡ n°³ÀÇ ¹ðÅ©µé Áß¿¡¼ ÇÑ°³¸¦ ÇÒ´çÇÑ´Ù. ±×·¯¸é, °¢ ÇÁ·Î¼¼½º´Â Àڽſ¡°Ô ÇÒ´çµÈ ¹ðÅ©»ó¿¡¼ ÁÖ·Î ¼öÇàµÇ¸ç, ±× ¹ðÅ©»ó¿¡¼´Â ¸¶Ä¡ direct-mapped ij½¬Ã³·³ µ¿À۵ȴÙ. ij½¬ ´ëÄ¡½Ã¿¡´Â °¡Àå ´Ê°Ô ½ºÄÉÁìµÉ ÇÁ·Î¼¼½ºÀÇ Ä³½¬¶óÀÎÀ» Èñ»ý ij½¬·Î ¼±Á¤Çϱ⠶§¹®¿¡ È¿°úÀûÀÎ ´ëÄ¡°¡ ÀÌ·ç¾î Áø´Ù. Æ®·¹À̽º ±¸µ¿ ¸ðÀÇ ½ÇÇè °á°ú´Â »õ·Î¿î ij½¬ ±¸Á¶°¡ set-associative ij½¬Ã³·³ ¸¹Àº Ãæµ¹½ÇÆа¡ Á¦°ÅµÉ»Ó ¾Æ´Ï¶ó ij½¬ ¾×¼¼½º ½Ã°£ÀÌ direct-mapped ij½¬Ã³·³ ºü¸£´Ù´Â °ÍÀ» º¸¿© ÁÖ°í ÀÖ´Ù. |
¿µ¹®³»¿ë (English Abstract) |
In this paper, we propose a new virtual cache architecture for fast RISC processors whose average access time is comparable to that of the direct-mapped cache while the hit ratio is the same as the set-associative cache. The entire cache memory is divided into n banks, and each process is assigned to a bank when it is created. Then, each process runs on the assigned bank, and the cache behaves like a direct-mapped cache. A victim for cache replacement is selected from those that belong to a process which is least likely to be scheduled in the near future. Results from trace-driven simulations confirm that the new scheme removes almost as many conflict misses as does the set-associative cache, while cache access time is similar to a direct-mapped cache. |
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