• Àüü
  • ÀüÀÚ/Àü±â
  • Åë½Å
  • ÄÄÇ»ÅÍ
´Ý±â

»çÀÌÆ®¸Ê

Loading..

Please wait....

¿µ¹® ³í¹®Áö

Ȩ Ȩ > ¿¬±¸¹®Çå > ¿µ¹® ³í¹®Áö > Journal of EEIS

Journal of EEIS

Current Result Document :

ÇѱÛÁ¦¸ñ(Korean Title) An Improved Ground Bounce-Free Output Butter
¿µ¹®Á¦¸ñ(English Title) An Improved Ground Bounce-Free Output Butter
ÀúÀÚ(Author) Sang-Hoon Lee   Yung-Kwon Sung  
¿ø¹®¼ö·Ïó(Citation) VOL 04 NO. 01 PP. 0008 ~ 0013 (1999. 02)
Çѱ۳»¿ë
(Korean Abstract)
¿µ¹®³»¿ë
(English Abstract)
In this paper, we propose an improved ground bounce-free output buffer. In order to reduce the ground bounce voltage, we suggest a new architecture of the ground bounce-free output buffer. It is to control the cut off and saturation mode of two N-MOS transistors in an output buffer with a time difference. The simulation results show the -0.7V ground bounce voltage at any condition. A fabricated sample using 0.6%u339B CMOS DLM process demonstrates the ground bounce noise level less than -0.7V at 0%u2103 degree. These results show the lower ground bounce noise than the conventional output buffer at the same output low voltage level(VOL). And also the average high-to-low propagation delay of 3.5ns is achieved. This figure is comparable to 3.6ns of the conventional output buffer.
Å°¿öµå(Keyword) Ground Bounce   CMOS Output Buffer   Delay Chain   Propagation Delay  
ÆÄÀÏ÷ºÎ PDF ´Ù¿î·Îµå