Journal of EEIS
Current Result Document :
| 한글제목(Korean Title) |
An On-chip Multiprocessor Microprocerssor with Shared MMU and Cache |
| 영문제목(English Title) |
An On-chip Multiprocessor Microprocerssor with Shared MMU and Cache |
| 저자(Author) |
Yong-Hwan Lee
Woo-Kyeong Jeong
Sang-Jun An
Yong-Surk Lee
|
| 원문수록처(Citation) |
VOL 02 NO. 04 PP. 0001 ~ 0007 (1997. 08) |
한글내용
(Korean Abstract) |
|
영문내용
(English Abstract) |
A multiprocessor microprocessor named SNPC(scaleable multiprocessor chip) that contains two IU(integer unit)ispresenter in this paper. It can execute multiple instrucitons from several tasks exploiting task-level parallelism that is free from instruction dependencies, and provide high performance and throughput on both single program and multiprogramming environments. The IU is a 32-bit scalar processor especially designed to boost up the performance of string manipulations which are frequintly used in RDBMS(relational data base management system) applications. A memory management unit and a data cache shared by two IUs improve the performance and reduce the chip area required. The SMPC is implemented in VLSI circuit by custom design and automated design tools. |
| 키워드(Keyword) |
CAD and VLSI Design
On-chip Multiprocessor
Microprocerssor
MMU
Cache
|
| 파일첨부 |
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