2012³â Ãá°èÇмú´ëȸ
Current Result Document :
ÇѱÛÁ¦¸ñ(Korean Title) |
PMIC¿ë 8ºñÆ® eFuse OTP Memory ¼³°è ¹× ÃøÁ¤ |
¿µ¹®Á¦¸ñ(English Title) |
Design of an eFuse OTP Memory of 8 Bits for PMICs and its Measurement |
ÀúÀÚ(Author) |
¹Ú¿µ¹è
ÃÖÀÎÈ
À̵¿ÈÆ
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ÀåÁöÇý
ÇÏÆǺÀ
±è¿µÈñ
Young-Bae Park
In-Hwa Choi
Dong-Hoon Lee
Liyan Jin
Ji-Hye Jang
Pan-Bong Ha
Young-Hee Kim
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¿ø¹®¼ö·Ïó(Citation) |
VOL 16 NO. 01 PP. 0722 ~ 0725 (2012. 05) |
Çѱ۳»¿ë (Korean Abstract) |
º» ³í¹®¿¡¼´Â ÇÁ·Î±×·¥ µÈ eFuse ¸µÅ©ÀÇ ¼¾½Ì ÀúÇ×ÀÌ ÀÛÀ¸¸é¼ ±âÁØ Àü¾Ð¾øÀÌ BL µ¥ÀÌÅ͸¦ ¼¾½Ì °¡´ÉÇÑ differential paired eFuse ¼¿À» »ç¿ëÇÏ¿© BCD °øÁ¤ ±â¹ÝÀÇ 8ºñÆ® eFuse OTP¸¦ ¼³°èÇÏ¿´´Ù. Differential eFuse OTP ¼¿ÀÇ ÇÁ·Î±×·¥ Æ®·£Áö½ºÅÍÀÇ Ã¤³Î ÆøÀº 45§°ú 120§À¸·Î splitÇÏ¿´´Ù. ±×¸®°í ÇÁ·Î±×·¥µÈ eFuse ÀúÇ×ÀÇ º¯µ¿À» °í·ÁÇÑ variable pull-up load¸¦ °®´Â ¼¾½Ì ¸¶Áø Å×½ºÅÍ(sensing margin test) ȸ·Î¸¦ ±¸ÇöÇÏ¿´´Ù. 0.35§ BCD °øÁ¤À» ÀÌ¿ëÇÏ¿© Á¦ÀÛµÈ 8bit eFuse OTP IP¸¦ ÃøÁ¤ÇÑ °á°ú ÇÁ·Î±×·¥ Æ®·£Áö½ºÅÍÀÇ Ã¤³Î ÆøÀÌ 120§ÀÎ OTP IPÀÇ ¼öÀ²ÀÌ 45§ÀÎ OTP IPº¸´Ù ¾çÈ£ÇÑ °ÍÀ¸·Î ³ªÅ¸³µ´Ù.
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¿µ¹®³»¿ë (English Abstract) |
In this paper, we design an 8-bit eSuse OTP (one-time programmable) memory based on a 0.35§ BCD process using differential paired eFuse cells which can sense BL data without a reference voltage and also have smaller sensing resistances of programmed eFuse links. The channel widths of a program transistor of the differential eFuse OTP cell are splitted into 45§ and 120§. Also, we implement a sensing margin test circuit with variable pull-up loads in consideration of variations of the programmed eFuse resistances. It is confirmed by measurement results that the designed 8-bit eFuse OTP memory IP gives a better yield when the channel width is 120§.
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Å°¿öµå(Keyword) |
Differential Paired eFuse OTP
BCD process
Variable pull-up loads
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ÆÄÀÏ÷ºÎ |
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