2009³â Ãß°èÇмú´ëȸ
Current Result Document :
ÇѱÛÁ¦¸ñ(Korean Title) |
½º¸¶Æ®Ä«µå¿ë HAS-160 ÇÁ·Î¼¼¼ ¼³°è |
¿µ¹®Á¦¸ñ(English Title) |
A Design of HAS-160 Processor for Smartcard Application |
ÀúÀÚ(Author) |
±èÇØÁÖ
½Å°æ¿í
Hae-ju Kim
Kyung-Wook Shin
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¿ø¹®¼ö·Ïó(Citation) |
VOL 13 NO. 02 PP. 0913 ~ 0916 (2009. 10) |
Çѱ۳»¿ë (Korean Abstract) |
º» ³í¹®¿¡¼´Â Çѱ¹Çü Ç¥ÁØ Çؽ¬ ¾Ë°í¸®µëÀÎ HAS-160À» ±¸ÇöÇÏ´Â ÇÁ·Î¼¼¼¸¦ ¼³°èÇÏ¿´´Ù. °¢ ´Ü°è¿¬»ê¿¡ »ç¿ëµÇ´Â 4°³ÀÇ °¡»ê±â´Â ¿¬»ê¼º´ÉÀ» ³ôÀ̱â À§ÇØ 5:3 ¹× 3:2 ij¸®º¸Á¸ °¡»ê±â(carry-save adder)¿Í ij¸®¼±Åà °¡»ê±â(carry-select adder)ÀÇ È¥ÇÕ±¸Á¶¸¦ »ç¿ëÇÏ¿´´Ù. ¼³°èµÈ HAS-160 ÇÁ·Î¼¼¼´Â 512 ºñÆ® ¸Þ½ÃÁö·ÎºÎÅÍ 160ºñÆ®ÀÇ Çؽ¬Äڵ带 »ý¼ºÇϴµ¥ 82 Ŭ·ÏÁֱⰡ ¼Ò¿äµÇ¸ç, 50 MHz@3.3-V·Î µ¿ÀÛÇÏ´Â °æ¿ì 312 MbpsÀÇ ¼º´ÉÀ» ³ªÅ¸³½´Ù. 0.35-§ CMOS ¼¿ ¶óÀ̺귯¸®·Î ÇÕ¼ºÇÑ °á°ú ¾à 17,600°³ÀÇ °ÔÀÌÆ®·Î ±¸ÇöµÇ¾ú´Ù.
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¿µ¹®³»¿ë (English Abstract) |
This paper describes a hardware design of hash processor which implements HAS-160 algorithm adopted as a Korean standard. To achieve a high-speed operation with small-area, the arithmetic operation is implemented using a hybrid structure of 5:3 and 3:2 carry-save adders and a carry-select adder. The HAS-160 processor synthesized with 0.35-§ CMOS cell library has 17,600 gates. It computes a 160-bit hash code from a message block of 512 bits in 82 clock cycles, and has 312 Mbps throughput at 50 MHz@3.3-V clock frequency.
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Å°¿öµå(Keyword) |
Hash algorithm
HAS-160
authentication
information security
smartcard
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ÆÄÀÏ÷ºÎ |
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