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Ȩ Ȩ > ¿¬±¸¹®Çå > Çмú´ëȸ ÇÁ·Î½Ãµù > Çѱ¹Á¤º¸Åë½ÅÇÐȸ Çмú´ëȸ > 2009³â Ãá°èÇмú´ëȸ

2009³â Ãá°èÇмú´ëȸ

Current Result Document :

ÇѱÛÁ¦¸ñ(Korean Title) ¿µ»ó Á¤º¸ÀÇ LDPC ºÎȣȭ ¹× º¹È£±âÀÇ FPGA±¸Çö
¿µ¹®Á¦¸ñ(English Title) LDPC Coding for image data and FPGA Implementation of LDPC Decoder
ÀúÀÚ(Author) ±èÁø¼ö   Á¦°¥µ¿   º¯°Ç½Ä   Jin Su Kim   Jaegal Dong   Kun Sik Byon  
¿ø¹®¼ö·Ïó(Citation) VOL 13 NO. 01 PP. 0888 ~ 0890 (2009. 05)
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(Korean Abstract)
ÀâÀ½ÀÌ Á¸ÀçÇϴ ȯ°æ¿¡¼­ ä³Î·Î Á¤º¸¸¦ Àü¼ÛÇϱâ À§Çؼ­´Â Á¤º¸¸¦ ºÎȣȭÇÏ´Â ±â¼úÀÌ ÇÊ¿äÇÏ´Ù. ¿À·ù °ËÃâ°ú Á¤Á¤¿¡ »ç¿ëµÇ´Â ¿©·¯ °¡Áö ºÎȣȭ ±â¼ú Áß ShannonÀÇ ÇÑ°è¿¡ °¡Àå ±ÙÁ¢ÇÑ ºÎȣȭ ±â¼úÀÌ LDPC ºÎÈ£ÀÌ´Ù. LDPC ºÎÈ£¿Í sum-product ¾Ë°í¸®µëÀÇ Á¶ÇÕ¿¡ ÀÇÇØ ¾ò¾îÁö´Â º¹È£ Ư¼ºÀº Åͺ¸ ºÎÈ£, RA(Repeat Accumulate) ºÎÈ£ÀÇ ¼º´É¿¡ ÇÊÀûÇϸç, ºÎÈ£ÀåÀÌ ¸Å¿ì ±ä °æ¿ì¿¡´Â ÀÌµé ¼º´ÉÀ» Ãß¿ùÇÑ´Ù. º» ³í¹®¿¡¼­´Â ¿µ»ó Á¤º¸ÀÇ LDPC ºÎȣȭ¿Í º¹È£È­ ±â¼ú ¿ø¸®¿¡ °üÇØ ¼³¸íÇÏ°í, Sum-product ¾Ë°í¸®µëÀ» »ç¿ëÇÏ´Â LDPC º¹È£±â¸¦ FPGA·Î ±¸ÇöÇÑ´Ù.
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(English Abstract)
To transmit information over a channel in the presence of noise, there needs some technique to code the information. One of the coding techniques used for error detection and correction close to the Shannon limit is Low Density Parity Code. LDPC and decoding characteristic features by sum-product algorithm are matched for the performance to Turbo Code, RA(Repeat Accumulate) code, in case of very long code length of LDPC surpass their performance. This paper explains LDPC coding scheme of image data and decoding scheme, implements LDPC decoder in FPGA.
Å°¿öµå(Keyword) LDPC   EEC   System Generator   FPGA  
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