Journal of EEIS
Current Result Document :
| 한글제목(Korean Title) |
Transformation and VHDL Code Generation from Coarse-grained Dataflow Graph |
| 영문제목(English Title) |
Transformation and VHDL Code Generation from Coarse-grained Dataflow Graph |
| 저자(Author) |
Moonwook Oh
Soonhoi Ha
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| 원문수록처(Citation) |
VOL 03 NO. 06 PP. 0736 ~ 0741 (1998. 12) |
한글내용
(Korean Abstract) |
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영문내용
(English Abstract) |
This paper discusses how we generate VHDL codes for DSP applications described in dataflow graphs. Because the generated VHDL code implements the details of the control structure, we can easily transform it into a running circuit without any modifications, using logic synthesis tools. To improve the quality of the synthesized circuit we apply some graph transformation techniques to the original dataflow graph. We mainly consider coarse-grained dataflow graphs in which each node corresponds to an IP component of considerable size. The proposed facility is very useful for dataflow graph based high level design tools, including our codesign framework PeaCE (Ptolemy extension as Codesign Environment).
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| 키워드(Keyword) |
VHDL
PeaCE
Transformation
Code Generation
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| 파일첨부 |
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