Journal of EEIS
Current Result Document :
| 한글제목(Korean Title) |
Lower Power Channel Routing by Crosstalk Minimization for Deep Submicron VLSI Design |
| 영문제목(English Title) |
Lower Power Channel Routing by Crosstalk Minimization for Deep Submicron VLSI Design |
| 저자(Author) |
Su-Hyun Nam
Jun-Dong Cho
|
| 원문수록처(Citation) |
VOL 04 NO. 06 PP. 0660 ~ 0667 (1999. 12) |
한글내용
(Korean Abstract) |
|
영문내용
(English Abstract) |
The channel routing problem we consider is to assign a set of nets given by horizontal segments to a set of tracks in the channel such that no two intervals assigned to the same track overlap. One important goal is to find a channel routing with the minimum number of tracks such that the signal interference between nets assigned to neighboring tracks is minimized, and thus power consumption is reduced and signal integrity is improved. This problem is called crosstalk-minimum channel routing. For a given net assignment with k tracks, crosstalk can be reduced by finding another net assignment for S with k tracks (i.e., by permuting nets in tracks). However, considering all possible permutations requires time. For general cost function for crosstalk measure, the problem is NP-hard. Several heuristic approaches were previously presented. In this paper, we consider special instances of the crosstalk-minimization problem where the cost function depends only on the length of the segments that runs in parallel. A fast near-optimal algorithm solving this problem in is presented. The channel routing uses a small number of 45wire patterns that leads to an efficient crosstalk-minimum channel routing. Experimental results showed the effectiveness of the proposed algorithm. |
| 키워드(Keyword) |
VLSI Layout
Crosstalk
Channel Routing
Deepsubmicron
Algorithm
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| 파일첨부 |
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