TIIS (한국인터넷정보학회)
Current Result Document :
| 한글제목(Korean Title) |
A Multi-Level Accumulation-Based Rectification Method and Its Circuit Implementation |
| 영문제목(English Title) |
A Multi-Level Accumulation-Based Rectification Method and Its Circuit Implementation |
| 저자(Author) |
Hyeon-Sik Son
Byungin Moon
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| 원문수록처(Citation) |
VOL 11 NO. 06 PP. 3208 ~ 3229 (2017. 06) |
한글내용
(Korean Abstract) |
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영문내용
(English Abstract) |
Rectification is an essential procedure for simplifying the disparity extraction of stereo matching algorithms by removing vertical mismatches between left and right images. To support real-time stereo matching, studies have introduced several look-up table (LUT)- and computational logic (CL)-based rectification approaches. However, to support high-resolution images, the LUT-based approach requires considerable memory resources, and the CL-based approach requires numerous hardware resources for its circuit implementation. Thus, this paper proposes a multi-level accumulation-based rectification method as a simple CL-based method and its circuit implementation. The proposed method, which includes distortion correction, reduces addition operations by 29%, and removes multiplication operations by replacing the complex matrix computations and high-degree polynomial calculations of the conventional rectification with simple multi-level accumulations. The proposed rectification circuit can rectify 1,280 × 720 stereo images at a frame rate of 135 fps at a clock frequency of 125 MHz. Because the circuit is fully pipelined, it continuously generates a pair of left and right rectified pixels every cycle after 13-cycle latency plus initial image buffering time. Experimental results show that the proposed method requires significantly fewer hardware resources than the conventional method while the differences between the results of the proposed and conventional full rectifications are negligible.
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| 키워드(Keyword) |
Rectification
multi-level accumulation
distortion correction
stereo vision
stereo matching
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| 파일첨부 |
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