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Ȩ Ȩ > ¿¬±¸¹®Çå > ±¹³» ³í¹®Áö > Çѱ¹Á¤º¸°úÇÐȸ ³í¹®Áö > Á¤º¸°úÇÐȸ³í¹®Áö (Journal of KIISE)

Á¤º¸°úÇÐȸ³í¹®Áö (Journal of KIISE)

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ÇѱÛÁ¦¸ñ(Korean Title) µ¥ÀÌÅÍ Àü¼ÛÀÌ ÃÖÀûÈ­µÈ °í¼öÁØ FPGA È£½ºÆ® ÇÁ·Î±×·¡¹Ö ÀÎÅÍÆäÀ̽º
¿µ¹®Á¦¸ñ(English Title) Data Transfer Optimized High-level FPGA Host Programming Interface
ÀúÀÚ(Author) ±Ç¼øÇö   À¯ÀçÇР  ¹Ú¼¼Áø   ÀüÁ¾¾Ï   ǥö½Ä   Soonhyun Kwon   Jaehak Yu   Sejin Park   Jongarm Jun   Cheol-Sig Pyo   ±èÁ¾¿ì   ¹Ú¼º¼ö   ÇÑȯ¼ö   Jongwoo Kim   Seongsoo Park   Hwansoo Han  
¿ø¹®¼ö·Ïó(Citation) VOL 48 NO. 08 PP. 0859 ~ 0864 (2021. 08)
Çѱ۳»¿ë
(Korean Abstract)
´Ù¾çÇÑ ¿öÅ©·Îµå¸¦ È¿À²ÀûÀ¸·Î ½ÇÇàÇϱâ À§ÇØ ¹ü¿ë CPU ÀÌ¿ÜÀÇ Çϵå¿þ¾î °¡¼Ó±â°¡ È°¿ëµÇ°í ÀÖ´Ù. ÃÖ±Ù C/C++ µîÀÇ °í¼öÁØ ¾ð¾î¸¦ »ç¿ëÇÏ¿© FPGA¸¦ °¡¼Ó±â·Î È°¿ëÇÒ ¼ö ÀÖµµ·Ï Áö¿øÇϸ鼭 ³Î¸®»ç¿ëµÇ¾î ¿Â GPU ÀÌ¿Ü¿¡µµ FPGA¸¦ ¼ÒÇÁÆ®¿þ¾î °³¹ß ºÐ¾ß¿¡¼­ »ç¿ëÇÏ´Â Ãß¼¼ÀÌ´Ù. OpenCLÀ» »ç¿ëÇÏ¿©´ëºÎºÐÀÇ À̱âÁ¾ ÇÁ·Î¼¼¼­ ÇÁ·Î±×·¥À» °³¹ßÇÒ ¼ö ÀÖÁö¸¸, ÇÁ·Î¼¼¼­¸¶´Ù ÃÖÀûÈ­ ¿ä¼Ò¿¡ Â÷ÀÌ°¡ ÀÖ´Ù. ƯÈ÷, FPGAÀÇ Ä¿³Î ÇÁ·Î±×·¥ °³¹ßÀº Ÿ À̱âÁ¾ ÇÁ·Î¼¼¼­º¸´Ù Çϵå¿þ¾î Ãø¸éÀÇ Áö½ÄÀÌ ¸¹ÀÌ ¿ä±¸µÇ¸ç, ÀÌ¿Í °°Àº Ư¼º ¶§¹®¿¡ Ä¿³Î»Ó¸¸ ¾Æ´Ï¶ó È£½ºÆ® ÇÁ·Î±×·¥¿¡¼­µµ ÃÖÀûÈ­¸¦ °í·ÁÇØ¾ß ÇÑ´Ù. º» ³í¹®¿¡¼­´Â FPGA¿ë È£½ºÆ® ÇÁ·Î±×·¥ °³¹ßÀ» À§ÇÑ °í¼öÁØ ÇÁ·Î±×·¡¹Ö ÀÎÅÍÆäÀ̽ºÀÎ SimFLÀ» Á¦¾ÈÇÏ¿´°í, SimFLÀ» »ç¿ëÇÏ¿© ±¸ÇöµÈ FPGA ¿ë È£½ºÆ® ÇÁ·Î±×·¥¿¡¼­ ´ÙÁß ¾²·¹µå¸¦ ÀÌ¿ëÇÏ´Â µ¥ÀÌÅÍ Àü¼Û ÃÖÀûÈ­ Àû¿ë¿¡ µû¸¥ ÃÖ´ë 44.7%ÀÇ ¼º´É Çâ»óÀ» °ËÁõÇÏ¿´´Ù.
¿µ¹®³»¿ë
(English Abstract)
Along with general-purpose CPUs, hardware accelerators have been widely adopted to execute various workloads efficiently. Recently, FPGAs have emerged in the area of software-level development as high-level languages such as C/C support FPGA programming. OpenCL supports most heterogeneous processors in high-level programming, but different optimization techniques are required depending upon the unique architectural features in the accelerators. In particular, developing FPGA kernel programs requires more knowledge of hardware architecture than other heterogeneous processors. Due to this characteristic, optimization should be collaborated with the host program as well. In this paper, we proposed SimFL, a high-level programming interface for developing host programs to use FPGAs as accelerators. To evaluate our optimization, we used the host programs for FPGA with SimFL and verified a performance improvement of up to 44.7% by applying multi-threaded copying within SimFL.
Å°¿öµå(Keyword) Áúȯ ¿¹Ãø   ÀÇÇÐÁö½Ä À¶ÇÕ   ÀÇÇÐÁö½Ä Ã߷Р  ¸Ó½Å·¯´×   µö·¯´×   »ýü½ÅÈ£ºÐ¼®   disease prediction   medical knowledge convergence   medical knowledge inference   machine learning   deep learning   bio-signal analysis   À̱âÁ¾ ÄÄÇ»Æà  FPGA È£½ºÆ® ÇÁ·Î±×·¥   ÇÁ·Î±×·¡¹Ö ÀÎÅÍÆäÀ̽º   µ¥ÀÌÅÍ Àü¼Û ÃÖÀûÈ­   heterogeneous computing   FPGA host program   programming interface   data transfer optimization  
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